DAC 2010 ANAHEIM JUNE 13-18
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7th Symposium on Electronic System-level Design with SystemC
Multi-Day Event
6th IEEE Symposium on Application Specific Processors
Multi-Day Event
Nanoarch '08: IEEE/ACM Symposium on Nanoscale Architectures
Multi-Day Event
Global Semiconductor Test Consortium Conference (GSC)
Multi-Day Event
MEMOCODE'2008: Sixth ACM-IEEE International Conference on Formal Methods and Models for Codesign
Multi-Day Event
High-level Synthesis: Back to the Future
SUNDAY - June 08, 8:30am - 5:30pm / 208A
5th International UML for SoC Design Workshop: UML in Application
SUNDAY - June 08, 9:00am - 6:00pm / 209A
System and SoC Debug
SUNDAY - June 08, 9:00am - 5:15pm / 303B - Lunch 303A
Biochips to Interface and Monitor Human Biological Functions
SUNDAY - June 08, 9:30am - 4:30pm / 210AB
Design and Verification of Low Power SoCs: An Application Oriented Approach
SUNDAY - June 08, 2:00pm - 5:00pm / 303C
Low Power Coalition Workshop – Advances in Low Power Design for Circuits and Systems
SUNDAY - June 08, 4:00pm - 7:00pm / 206B
EDA Consortium Executive Reception
SUNDAY - June 08, 4:30pm - 7:30pm / Anaheim Hilton Hotel / Pacific Ballroom
Cross-layer Power and Thermal Management
MONDAY - June 09, 8:30am - 4:30pm / 212A
IEEE International Workshop on Hardware-oriented Security and Trust (HOST-2008)
MONDAY - June 09, 8:30am - 5:45pm / 204A
#1 - Bridging a Verification Gap: C++ to RTL for Practical Design
MONDAY - June 09, 9:00am - 5:00pm / 210AB
#2 - Programming Massively Parallel Processors: the NVIDIA Experience
MONDAY - June 09, 9:00am - 5:00pm / 209AB
Elevating Confidence in Design IP Through Mutation-based Analysis Technology - Certess, Inc. / STMicroelectronics / Brian Bailey Consulting
MONDAY - June 09, 9:00am - 12:00pm / 213D
Women in Design Automation: Networking, Negotiation, and Nonsense: Achieving Career Balance in an Unbalanced World
MONDAY - June 09, 9:00am - 1:45pm / 205A
Diagnostic Services in Network-on-Chips (DSNOC)
MONDAY - June 09, 9:00am - 5:00pm / 303AB
Design Automation Day for High School Students
MONDAY - June 09, 9:15am - 10:15am / 202A
Gary Smith on EDA: Trends and What’s Hot at DAC
MONDAY - June 09, 9:30am - 10:30am / Booth #364
Introduction to Chips and EDA for a Non-technical Audience
MONDAY - June 09, 10:00am - 12:00pm / 206B
Presented by Mentor Graphics Corp.: Object Oriented Hardware Reuse with ANSI C+++ and Algorithmic Synthesis
MONDAY - June 09, 10:10am - 10:50am / Exhibit Hall D, Booth 2849
EDA Heritage Series: Maxwell’s Legacy
MONDAY - June 09, 10:45am - 11:45am / Booth #364
Presented by Mentor Graphics Corp.: What you Should Know about The Open Verification Methodology (OVM)
MONDAY - June 09, 10:50am - 11:30am / Exhibit Hall D, Booth 2849
Student Design Contest Award Presentation
MONDAY - June 09, 12:00pm - 1:00pm / Booth #364
4th Integrated Design Systems Workshop - OpenAccess: A Platform for Continuous Evolution and Innovation
MONDAY - June 09, 12:00pm - 4:00pm / 208A
ADDITIONAL MEETING: Interoperable PDK Libraries – The Proof is in the Pudding!
MONDAY - June 09, 12:00pm - 1:30pm / Ballroom D
ADDITIONAL MEETING: ACM/SIGDA Symposia/Workshop and Technical Committee Leaders Luncheon
MONDAY - June 09, 12:00pm - 2:00pm / 201B
Doulos Solutions Workshop 1 with Cadence - "Migrating to OVM for Multi-language Verification-How to Enable VIP Inter-operability"
MONDAY - June 09, 12:15pm - 2:00pm / 201A
Beyond Syntax and Semantics: Industry Experiences with OVL/SVA/PSL
MONDAY - June 09, 1:00pm - 5:15pm / 207D
Next Generation Data Centers: Environmentally Green, Financially Green
MONDAY - June 09, 2:00pm - 2:45pm / Booth #364
2007 ACM Turing Award Winners
MONDAY - June 09, 2:00pm - 4:00pm / Ballroom ABC
Presented by Magma Design Automation: Titan™ Chip Finishing and Faster Analog Design Implementation/Migration
MONDAY - June 09, 2:00pm - 2:40pm / Exhibit Hall D, Booth 2849
Presented by Mentor Graphics Corp.: Mentor Graphics and Agilent Technologies Integrated RF Design Solution for PCBs
MONDAY - June 09, 2:40pm - 3:20pm / Exhibit Hall D, Booth 2849
Today’s Consumers: High Schoolers Spec Your Next Product
MONDAY - June 09, 3:00pm - 3:45pm / Booth #364
Presented by Denali Software, Inc.: Key Ingredients of a Next-generation NAND Flash Platform
MONDAY - June 09, 3:20pm - 4:00pm / Exhibit Hall D, Booth 2849
Will 22nm Be Our Catch-22?
MONDAY - June 09, 4:00pm - 5:00pm / Booth #364
ADDITIONAL MEETING: Si2 Members Meeting
MONDAY - June 09, 6:00pm - 8:00pm / 304B
ADDITIONAL MEETING: IP-XACT 1.4 in Action: Open Public Meeting of the SPIRIT Consortium
MONDAY - June 09, 6:00pm - 9:00pm / Ballroom A
ADDITIONAL MEETING: Synopsys/Sun University Reception
MONDAY - June 09, 6:00pm - 8:00pm / Marriott-Platinum3&4
EDA for Digital, Programmable, Multi-radios
TUESDAY - June 10, 8:30am - 10:15am / Ballroom ABC
Management Day at 45th Design Automation Conference
TUESDAY - June 10, 8:30am - 6:00pm / 204BC
Effective Technical Writing
TUESDAY - June 10, 10:00am - 12:00pm / 212A
ADDITIONAL MEETING: Seminar on Automatic Generation of Models for CoWare Platform Architect
TUESDAY - June 10, 10:00am - 11:00am / 202B
Session 1: iDesign I
TUESDAY - June 10, 10:30am - 12:00pm / 206AB
Session 2: SPECIAL SESSION: Enabling Concurrency in EDA
TUESDAY - June 10, 10:30am - 12:00pm / 207ABC
Session 3: CAD for FPGA
TUESDAY - June 10, 10:30am - 12:00pm / 208AB
Session 4: Analog Performance Modeling and Synthesis
TUESDAY - June 10, 10:30am - 12:00pm / 209AB
Session 5: Novel Techniques in Embedded Processor Design
TUESDAY - June 10, 10:30am - 12:00pm / 210AB
Session 6: Electronics and Politics: What the Industry Needs From the Incoming US Administration
TUESDAY - June 10, 10:30am - 12:00pm / 210CD
45nm: Collaborate, Aggregate, Differentiate
TUESDAY - June 10, 10:30am - 11:15am / Booth #364
Accellera Technical Committee Update and Technical Excellence Award
TUESDAY - June 10, 11:00am - 1:00pm / Exhibit Hall D, Booth2849
EDA: A View From Sand Hill Road
TUESDAY - June 10, 11:30am - 12:15pm / Booth #364
IEEE Council on EDA's Distinguished Speaker Lecture and Lunch
TUESDAY - June 10, 12:00pm - 2:00pm / 303AB
ADDITIONAL MEETING: Verification Luncheon
TUESDAY - June 10, 12:00pm - 2:00pm / Marriott-Ballroom E
Multi-processor SoCs: The Next Generation
TUESDAY - June 10, 1:00pm - 1:45pm / Booth #364
Session 7: Student Design Contest
TUESDAY - June 10, 2:00pm - 4:00pm / 206AB
Session 8: Reinventing EDA with Manycore Processors
TUESDAY - June 10, 2:00pm - 3:00pm / 207ABC
Session 9: Formal Verification Technology
TUESDAY - June 10, 2:00pm - 4:00pm / 208AB
Session 10: Layout Techniques for Modern Chip Designs
TUESDAY - June 10, 2:00pm - 4:00pm / 209AB
Session 11: Application Mapping and Power Efficiency
TUESDAY - June 10, 2:00pm - 4:00pm / 210AB
Session 12: Variation-aware Design
TUESDAY - June 10, 2:00pm - 4:00pm / 210CD
IP Selection: The Good, The Bad, and The Ugly
TUESDAY - June 10, 2:00pm - 2:45pm / Booth #364
Advanced Methodologies in Validating and Integrating High Speed Serial Interconnects in the Ultra Deep Sub-micron CMOS Era - Synopsys, Inc. / Open-Silicon, Inc.
TUESDAY - June 10, 2:00pm - 5:00pm / 213D
ADDITIONAL MEETING: IP-XACT User’s Group
TUESDAY - June 10, 2:00pm - 4:00pm / 201A
Presented by Mentor Graphics Corp.: 2-D and 3-D Variability Optimization
TUESDAY - June 10, 2:00pm - 2:40pm / Exhibit Hall D, Booth 2849
Presented by Mentor Graphics Corp.: Multi-Corner-Multi-Mode P&R for Timing, Power, and SI Closure
TUESDAY - June 10, 2:40pm - 3:20pm / Exhibit Hall D, Booth 2849
Session 8: Multi-core SoC Design is the Challenge! What is the Solution?
TUESDAY - June 10, 3:00pm - 4:00pm / 207ABC
EDA Globalization: Third World or New World?
TUESDAY - June 10, 3:00pm - 3:45pm / Booth #364
Presented by Blaze DFM, Inc.: Leakage Power Reduction using Electrical DFM Techniques (customer case study)
TUESDAY - June 10, 3:20pm - 4:00pm / Exhibit Hall D, Booth 2849
Quality Versus Time to Market: The Unmentionable Tradeoff
TUESDAY - June 10, 4:00pm - 4:45pm / Booth #364
Presented by CoFluent Design: Early Decision Trade-off, Addressing Performance Concerns in Future Network Infrastructure
TUESDAY - June 10, 4:00pm - 4:30pm / Exhibit Hall D, Booth 2849
Session 13: iDesign II
TUESDAY - June 10, 4:30pm - 6:00pm / 206AB
Session 14: Multi-core Simulation, Mixed-signal Power Optimization and Nanodevices
TUESDAY - June 10, 4:30pm - 6:00pm / 207ABC
Session 15: Experiences and Advances in Formal and Dynamic Verification
TUESDAY - June 10, 4:30pm - 6:00pm / 208AB
Session 16: Emerging Nano/Biotechnologies
TUESDAY - June 10, 4:30pm - 6:00pm / 209AB
Session 17: Cache Optimization and Embedded Systems Modeling
TUESDAY - June 10, 4:30pm - 6:00pm / 210AB
Session 18: ESL Hand-off: Fact or EDA Fiction?
TUESDAY - June 10, 4:30pm - 6:00pm / 210CD
SOI: Fact, Future and Fiction
TUESDAY - June 10, 5:00pm - 5:45pm / Booth #364
ADDITIONAL MEETING: Raiders of the Locked Art: Opening the Treasure with Interoperable PDK - Synopsys Interoperability Breakfast
WEDNESDAY - June 11, 7:30am - 9:30am / Marriott-Marquis
Accellera Breakfast and Panel Discussion: "Save Money Now! How to Reduce Costs, Complexity and Time to Market"
WEDNESDAY - June 11, 8:30am - 9:30am / 303D
Session 19: Analytical Modeling and Simulation of Complex Processing Systems
WEDNESDAY - June 11, 9:00am - 11:00am / 206AB
Session 20: Wild and Crazy Ideas
WEDNESDAY - June 11, 9:00am - 11:00am / 207ABC
Session 21: Next Generation Wireless-multimedia Devices - Who is up for the Challenge?
WEDNESDAY - June 11, 9:00am - 11:00am / 208AB
Session 22: Diagnosis and Debug
WEDNESDAY - June 11, 9:00am - 11:00am / 209AB
Session 23: Architectural and Precision Optimization in High-level Synthesis
WEDNESDAY - June 11, 9:00am - 11:00am / 210AB
Session 24: Extraction, Interconnect and Timing
WEDNESDAY - June 11, 9:00am - 11:00am / 210CD
ADDITIONAL MEETING: Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design
WEDNESDAY - June 11, 9:00am - 10:00am / Anaheim Hilton - El Capitan AB
Presented by Pyxis Technology, Inc.: Pyxis High Performance Yield-Aware IC Router
WEDNESDAY - June 11, 9:15am - 9:55am / Exhibit Hall D, Booth 2849
Hogan’s Heroes - Behavioral Synthesis: Is That Light at the End of the Tunnel an Oncoming Train?
WEDNESDAY - June 11, 9:30am - 10:30am / Booth #364
Presented by Teklatech: IR Drop and Noise Aware SoC Floorplanning
WEDNESDAY - June 11, 9:55am - 10:35am / Exhibit Hall D, Booth 2849
Presented by Tela Innovations, Inc.: 45nm Leakage Reduction Using Gridded, One Dimensional Layout
WEDNESDAY - June 11, 10:35am - 11:15am / Exhibit Hall D, Booth 2849
Challenges on Design Complexities for Advanced Wireless Silicon Systems
WEDNESDAY - June 11, 11:15am - 12:15pm / Ballroom ABC
ADDITIONAL MEETING: 6th Annual ESL Symposium - Finding the Common Ground on Successful ESL Methodologies: Views from Industry Experts
WEDNESDAY - June 11, 12:00pm - 2:00pm / Ballroom E
Doulos Solutions Workshop 2 with Mentor Graphics - "Getting Real with OVM, a True Open Source Verification Standard"
WEDNESDAY - June 11, 12:15pm - 2:00pm / 201A
ADDITIONAL MEETING: ACM TODAES Editorial Board Luncheon
WEDNESDAY - June 11, 12:30pm - 2:00pm / 204B
Advanced Low Power Techniques: Is Your Design Method Too Powerful?
WEDNESDAY - June 11, 1:00pm - 2:00pm / Booth #364
Session 25: Architectures for On-chip Communication
WEDNESDAY - June 11, 2:00pm - 4:00pm / 206AB
Session 26: CMOS Gate Modeling for Timing, Noise, and Power: Rapidly Changing Paradigm
WEDNESDAY - June 11, 2:00pm - 4:00pm / 207ABC
Session 27: Advanced Wireless Design
WEDNESDAY - June 11, 2:00pm - 4:00pm / 208AB
Session 28: Manufacturing Aware Design and Design Aware Manufacturing
WEDNESDAY - June 11, 2:00pm - 4:00pm / 209AB
Session 29: Advances in Sequential Optimization
WEDNESDAY - June 11, 2:00pm - 4:00pm / 210AB
Session 30: Verifying Really Complex Systems: On Earth and Beyond
WEDNESDAY - June 11, 2:00pm - 4:00pm / 210CD
Presented by Azuro, Inc.: Clock Implementation for Nanometer Chip Design
WEDNESDAY - June 11, 2:00pm - 2:40pm / Exhibit Hall D, Booth 2849
DFM Design Rules: Worth The Effort?
WEDNESDAY - June 11, 2:30pm - 3:15pm / Booth #364
Presented by Synfora, Inc.: Architectural Exploration for Low Power Design using PICO Extreme
WEDNESDAY - June 11, 2:40pm - 3:20pm / Exhibit Hall D, Booth 2849
Presented by Sequence Design, Inc.: Design for Power
WEDNESDAY - June 11, 3:20pm - 4:00pm / Exhibit Hall D, Booth 2849
Designing the New-generation Wireless Platform: Lessons from iPhone and Android
WEDNESDAY - June 11, 3:30pm - 4:30pm / Booth #364
Session 31: Beyond the Die - Packaging and Die Stacking
WEDNESDAY - June 11, 4:30pm - 6:00pm / 206AB
Session 32: ESL Methodologies for Platform-based Synthesis
WEDNESDAY - June 11, 4:30pm - 6:00pm / 207ABC
Session 33: Wireless: Business Meets Technology
WEDNESDAY - June 11, 4:30pm - 6:00pm / 208AB
Session 34: Leakage Analysis and Optimization
WEDNESDAY - June 11, 4:30pm - 6:00pm / 209AB
Session 35: Design Methods for On-chip Communication
WEDNESDAY - June 11, 4:30pm - 6:00pm / 210AB
Session 36: Keeping Hot Chips Cool: Are IC Thermal Problems Hot Air?
WEDNESDAY - June 11, 4:30pm - 6:00pm / 210CD
Best of DAC Award Winners
WEDNESDAY - June 11, 4:30pm - 5:00pm / Booth #2849
What's Holding Back Analog Design Automation?
WEDNESDAY - June 11, 5:00pm - 5:45pm / Booth #364
ADDITIONAL MEETING: Birds-of-a-Feather (BOF)
WEDNESDAY - June 11, 6:00pm - 7:30pm / 201C
CANDE Meeting
WEDNESDAY - June 11, 6:00pm - 7:00pm / 204A
ADDITIONAL MEETING: New Media: What Does It Mean and How Have We Started To Use It To Reach Our Decision Makers?
THURSDAY - June 12, 8:00am - 9:00am / 207D
ADDITIONAL MEETING: EDS Fair Breakfast Briefing
THURSDAY - June 12, 8:00am - 8:45am / 204C
Session 37: New Advances in Logic Synthesis
THURSDAY - June 12, 9:00am - 11:00am / 206AB
Session 38: 3-D Semiconductor Integration and Packaging
THURSDAY - June 12, 9:00am - 11:00am / 207ABC
Session 39: Statistical Timing Analysis
THURSDAY - June 12, 9:00am - 11:00am / 208AB
Session 40: Performance Driven Layout Optimization
THURSDAY - June 12, 9:00am - 11:00am / 209AB
Session 41: Power and Thermal Considerations in Single- and Multi-core Systems
THURSDAY - June 12, 9:00am - 11:00am / 210AB
Session 42: Multi-core Design Tools and Architectures
THURSDAY - June 12, 9:00am - 11:00am / 210CD
Hardened DDR PHY Integration - Denali Software, Inc. / SiSoft
THURSDAY - June 12, 9:00am - 12:00pm / 213D
Negotiating a Successful Career
THURSDAY - June 12, 10:00am - 10:45am / Booth #364
Your Functional Verification Roadmap: OVM, VMM, or Roll Your Own?
THURSDAY - June 12, 11:00am - 11:45am / Booth #364
Doulos Solutions Workshop 3 with Synopsys and ARM - "Delivering Ultra Low Power Solutions on the ARM Cortex-M3"
THURSDAY - June 12, 11:00am - 12:45pm / 201A
Idea to Implementation: A Different Perspective on System Design
THURSDAY - June 12, 12:45pm - 1:45pm / Ballroom ABC
Session 43: Reconfigurable Architecture Optimizations
THURSDAY - June 12, 2:00pm - 4:00pm / 206AB
Session 44: Formal Verification: Dude or Dud? Experiences from the Trenches
THURSDAY - June 12, 2:00pm - 4:00pm / 207ABC
Session 45: Random Topics in Testing
THURSDAY - June 12, 2:00pm - 4:00pm / 208AB
Session 46: Securing and Debugging Embedded Systems
THURSDAY - June 12, 2:00pm - 4:00pm / 209AB
Session 47: Topics in Power and Thermal Management
THURSDAY - June 12, 2:00pm - 4:00pm / 210AB
Session 48: DFM in Practice: Hit or Hype
THURSDAY - June 12, 2:00pm - 4:00pm / 210CD
Maximizing Efficiency in the Development Cycle
THURSDAY - June 12, 2:00pm - 4:00pm / 303A
Session 49: Physical Effects of Variability
THURSDAY - June 12, 4:30pm - 6:00pm / 206AB
Session 50: Soft Error in Scaled CMOS Design
THURSDAY - June 12, 4:30pm - 6:00pm / 207ABC
Session 51: Advances in Verification of Abstract (pre-RTL) Models
THURSDAY - June 12, 4:30pm - 6:00pm / 208AB
Session 52: Design Space Exploration
THURSDAY - June 12, 4:30pm - 6:00pm / 209AB
Session 53: Noise Reliability Enhancement
THURSDAY - June 12, 4:30pm - 6:00pm / 210AB
Session 54: Custom is from Mars and Synthesis from Venus
THURSDAY - June 12, 4:30pm - 6:00pm / 210CD
#3 - Robust Analog/Mixed-signal Design
FRIDAY - June 13, 9:00am - 5:00pm / 208AB
#4 - DFM Revisited: A Comprehensive Analysis of Variability at all Levels of Abstraction
FRIDAY - June 13, 9:00am - 5:00pm / 210AB
#5 - Low Power Techniques for SoC Design
FRIDAY - June 13, 9:00am - 5:00pm / 209AB
#6 - System Level Design for Embedded Systems
FRIDAY - June 13, 9:00am - 5:00pm / 210CD
IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation