DAC 2010 ANAHEIM JUNE 13-18
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DAC Archive

High-level Synthesis: Back to the Future
SUNDAY - June 08, 8:30am - 5:30pm / 208A

Session 3: CAD for FPGA
TUESDAY - June 10, 10:30am - 12:00pm / 208AB

Session 23: Architectural and Precision Optimization in High-level Synthesis
WEDNESDAY - June 11, 9:00am - 11:00am / 210AB

Hogan’s Heroes - Behavioral Synthesis: Is That Light at the End of the Tunnel an Oncoming Train?
WEDNESDAY - June 11, 9:30am - 10:30am / Booth #364

Session 26: CMOS Gate Modeling for Timing, Noise, and Power: Rapidly Changing Paradigm
WEDNESDAY - June 11, 2:00pm - 4:00pm / 207ABC

Session 29: Advances in Sequential Optimization
WEDNESDAY - June 11, 2:00pm - 4:00pm / 210AB

Session 37: New Advances in Logic Synthesis
THURSDAY - June 12, 9:00am - 11:00am / 206AB

Session 43: Reconfigurable Architecture Optimizations
THURSDAY - June 12, 2:00pm - 4:00pm / 206AB

Session 54: Custom is from Mars and Synthesis from Venus
THURSDAY - June 12, 4:30pm - 6:00pm / 210CD

IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation