DAC 2010 ANAHEIM JUNE 13-18
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DAC Archive

Presented by - IBM Corp.: Get Your Silicon Design Right the First Time
MONDAY - July 27, 1:00pm - 1:30pm / ICDC Stage - North Hall

Chip Modeling and Estimation: Preventing Design Failure Through Power Analysis for IP and Chip Designs
MONDAY - July 27, 2:00pm - 4:00pm / Booth #4359

ADDITIONAL MEETING: Panel: Frontiers in Verification: Coverage, Closure and Beyond
TUESDAY - July 28, 7:30am - 9:00am / Room: 309

ADDITIONAL MEETING: Synopsys, Inc. Verification Luncheon
TUESDAY - July 28, 12:00pm - 2:00pm / Marriott Hotel, Yerba Buena Salon 7

Presented by - Amiq Consulting S.R.L.: DVT Eclipse for Advanced e and SystemVerilog Programming
TUESDAY - July 28, 1:00pm - 1:30pm / ICDC Stage - North Hall

Design for X: Test, Power, and Design Validation
TUESDAY - July 28, 3:00pm - 5:00pm / Booth #4359

Verification: A Front-End Perspective
TUESDAY - July 28, 4:30pm - 6:00pm / Room: 132

Verifying an SOC Monster: Whose Job Is it Anyway?
TUESDAY - July 28, 4:30pm - 6:00pm / Room: 133

ADDITIONAL MEETING: Synopsys Interoperability Breakfast: VMM & IPL
WEDNESDAY - July 29, 7:30am - 9:30am / Marriott Hotel, Yerba Buena Salon 7

Speed Path Identification and Silicon Debug
WEDNESDAY - July 29, 9:00am - 11:00am / Room: 130

Jumping the High-Level Verification Hurdle
WEDNESDAY - July 29, 2:00pm - 4:00pm / Room: 130

Seeking the Holy Grail of Verification Coverage Closure
WEDNESDAY - July 29, 2:00pm - 2:45pm / Booth #1928

Verification and Debug: RTL, TLM and Formal Techniques
WEDNESDAY - July 29, 3:00pm - 5:00pm / Booth #4359

Advances in Core Verification Techniques
WEDNESDAY - July 29, 4:30pm - 6:00pm / Room: 130

The Tool Shows That My Design is Wrong, But Where is the Bug?
THURSDAY - July 30, 9:00am - 11:00am / Room: 133

Targeted Test and Diagnosis
THURSDAY - July 30, 9:00am - 11:00am / Room: 125

#3: Post-Silicon Validation and Runtime Verification: Ensuring Correctness after First Silicon
FRIDAY - July 31, 9:00am - 5:00pm / Room: 131

#6: Functional Verification Planning and Management: Navigating from Specification to Functional Closure
FRIDAY - July 31, 9:00am - 5:00pm / Room: 133

IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation