DAC 2012 SAN FRANCISCO JUNE 3-7
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Blue Pearl Joins Xilinx Alliance Program, Accelerates Design Implementation

May 29, 2012

SANTA CLARA, California–May 29, 2012 -Blue Pearl Software, Inc., a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, announced that it has joined the Xilinx Alliance Program. Xilinx Inc. is the worldwide leader and developer of All Programmable devices. As a result of its Xilinx collaboration, Blue Pearl announces improved productivity for Xilinx Vivado™ Design Suite users, by reducing development time, run time and the number of design iterations.
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Calypto Leverages Core Technology to Expand Product Portfolio, Announces Catapult Low-Power High-Level Synthesis

May 29, 2012

SANTA CLARA, Calif., – May 29, 2012 – Calypto® Design Systems, Inc., a leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) low power optimization, today announced Catapult® Low-Power (LP), the industry's first production quality, high-level synthesis (HLS) tool that adds power as an optimization goal. By leveraging Calypto’s existing best in class power analysis and optimization technology, Catapult LP provides a closed loop optimization across power, performance and area (PPA) to address the challenges of power-aware design.
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Real Intent Leads in Speed, Capacity and Precision with New Releases of Ascent Lint and Meridian CDC Verification Tools; Demos Set for 49th DAC

May 29, 2012

SUNNYVALE, Calif. – May 29, 2012 - Real Intent, Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today the release of version 4.1 of its Meridian™ Clock Domain Crossing (CDC) analyzer and the release of version 1.5.1 of its Ascent™ Lint tool. These new releases provide significant advances over the 2011 versions of the software.
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Flexras Technologies Announces Breakthrough Automatic Partitioning Tool

May 29, 2012

SAN FRANCISCO, CA– Design Automation Conference (DAC) – May 29, 2012 – Flexras Technologies, an EDA company specializing in partitioning for FPGA-based prototyping, today announced Wasga Compiler, a software tool that boosts multi-FPGA design performance. Wasga Compiler is unique and is the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. It typically delivers a 10X clock frequency increase, runs blazingly fast, handles multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board, whether it’s off-the-shelf or custom.
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Silicon Frontline Adds New Capabilities; Focuses on Semiconductor Power Device Reliability and Efficiency, Accurate 3D Parasitic Extraction, Point-to-Point Resistance

May 25, 2012

Campbell, CA – May 24, 2012 – Silicon Frontline Technology, Inc. (SFT) an Electronic Design Automation (EDA) company, in the 3D parasitic extraction and analysis software market, announced new versions of its flagship products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures, and a new product P2P (Pont-to-Point) for IR drop analysis.
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Cortus Launches APS3R 32 bit Microcontroller IP Core for Low Energy Embedded Applications

May 24, 2012

Montpellier, France, 22nd May 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the release of the latest member of their processor family: the energy efficient APS3R. The APS3R builds on experience with the earlier APS3 core but delivers improved computational performance. For more demanding embedded applications a dual core configuration is possible.
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MOSIS to offer highly efficient Cortus APS3R microcontroller core to System on Chip (SoC) designers

May 24, 2012

Montpellier, France and Marina del Rey, California, 24th May 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP and MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, announced the signing of a sales representative agreement. Under the agreement, MOSIS will offer the Cortus APS3R and associated peripherals to their customers. The deal will support the licensing of Cortus IP from design through prototyping to volume production with MOSIS.
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APACHE DESIGN RELEASES FOURTH-GENERATION REDHAWK FOR SUB-20 NANOMETER POWER SIGN-OFF

May 23, 2012

Pittsburgh – May 1, 2012 – ANSYS (NASDAQ: ANSS) subsidiary Apache Design, Inc. today introduced RedHawk™-3DX to meet the power, performance and price demands of low-power mobile, high-performance computing, consumer and automotive electronics. This fourth-generation power sign-off solution delivers greater accuracy, capacity and usability for full-chip dynamic power and reliability simulation to manage power consumption and improve power delivery efficiency of advanced integrated circuit (IC) designs.
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Pulsic to Introduce Place and Route Implementation Solution for Analog and Custom Digital Design at DAC 2012

May 22, 2012

SAN JOSE, CALIF., May 22, 2012 -- Following up on the Pulsic Planning Solution™ products introduced last year at DAC, Pulsic, the premier provider of physical design tools for precision design automation, will introduce a place-and-route implementation solution at DAC 2012 in San Francisco. The Pulsic Implementation Solution™ builds on the work of the planning tools, providing designers with easy-to-use, guided flows to automatically implement precise, hand-crafted quality design layouts with the highest routing completion and accuracy on the market.
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Docea Ships New Version of Power and Thermal Analysis Software,

May 22, 2012

SAN FRANCISCO, CA--Design Automation Conference (DAC) --May 22, 2012 - Docea Power, the design-for-low-power company that delivers Electronic System Level (ESL) software tools for power and thermal analysis and modelling, announced that it is shipping Aceplorer™ 3.0 with an event scheduler for enhanced scenario creation capabilities and support for thermal models generated by its AceThermalModeler for coupled power and thermal simulations capabilities. In addition, it is announcing AceThermalModeler™ 1.1 with an enhanced 3D viewer for fast model debugging.
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Real Intent’s Focus on Excellent Tools for Early Functional Verification & Advanced Sign-Off for Circuit Design Results in Over 35% Revenue Growth in First Half of 2012

May 22, 2012

Sunnyvale, California – May 21, 2012 –Real Intent Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today that that the company’s revenue in the first half of fiscal 2012 increased more than 35% when compared to the last half of fiscal 2011 and the company is on track to have an annual growth of over 100% by the end of 2012. In addition, the company’s customer list grew by over 30%, adding major semiconductor companies in storage, computing, networking, communications and consumer electronics industries.
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Etron Selects Berkeley Design Automation Analog FastSPICE™ Platform

May 21, 2012

SANTA CLARA, CA, —May 22, 2012— Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that Etron Technology, Inc., a world-class fabless IC design and product company specializing in specialty memory and system chips, has selected the company’s Analog FastSPICE™ (AFS) Platform for characterization and verification of their memory designs for low-power and consumer applications.
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IC Manage Introduces Views™ Storage Acceleration Software

May 16, 2012

IC Manage, Inc. today introduced its IC Manage Views™ storage acceleration software - a version aware, virtual file system that presents complete workspace views, while only transferring data on demand to a local file cache.
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IC Manage Releases 4th Annual Global Design Management Survey Results

May 16, 2012

IC Manage, Inc. today announced the availability of its fourth annual “Global Design Management Report”, which covers the results of a 524 respondent survey of IC design professionals.
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ICScape™ Grows Globally

May 15, 2012

Santa Clara, California – May 14, 2012 – ICScape Inc. today announced that after enabling over 100 successful customer tapeouts, it is now ready to market its solutions worldwide. The expansion is driven by US$28 million in financial backing the company received in 2011, mostly from China Electronics Corporation (CEC), China’s largest electronics conglomerate with 2011 revenue of over US$23 billion.
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ICScape™ Products Go Global

May 15, 2012

Santa Clara, California – May 14, 2012 – ICScape Inc. today announced the global availability of its EDA solutions that accelerate design closure. The products are silicon-proven, offering scalability, high value and enabling up to 50% reduction in time-to-closure.
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Sagantec Announces nmigrate™

May 15, 2012

SANTA CLARA, California – May 14, 2012 – Sagantec announced today its nmigrate layout migration and optimization tool specifically developed for 28nm and 20nm technology rules. nmigrate is based on the patented 2D dynamic compaction technology developed by NP-Komplete Technologies, whose acquisition Sagantec announced earlier this month. nmigrate has already been used successfully by several tier-1 semiconductor companies.
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Graham Bell Joins Real Intent to Promote Early Functional Verification & Advanced Sign-off Circuit Design Software

May 8, 2012

Sunnyvale, California – May 7, 2012 –Real Intent Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today that Graham Bell joined the company as Sr. Director of Marketing. Mr. Bell, an experienced Electronic Design Automation (EDA) marketing strategist, previously was Director of Business Development at IBSystems, which includes EDACafé. At Real Intent, he is responsible for corporate marketing, public relations, and industry partnerships, and reports to the president and CEO, Prakash Narain.
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Sagantec acquires NP-Komplete Technologies

May 3, 2012

Santa Clara, California – May 3, 2012 – Sagantec today announced that it has acquired Dutch startup NP-Komplete Technologies BV (Eindhoven, The Netherlands) for its physical design compaction and migration solutions based on a sophisticated 2D dynamic compaction technology. NP-Komplete Technologies (NPKT) is a provider of innovative DFM solutions, and physical design optimization engines. Terms of the acquisition are confidential.
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Samsung Electronics Tapes out Gigahertz+ ARM Cortex-A15 Processor with Synopsys IC Compiler

May 1, 2012

MOUNTAIN VIEW, Calif.—April 30, 2012—Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the successful collaboration between Synopsys and Samsung Electronics on the implementation of an ARM Cortex-A15 MPCore™ processor. The processor core was implemented by Samsung Austin Research Center (SARC) using Synopsys IC Compiler place-and-route technology, a cornerstone of the Synopsys Galaxy™ Implementation Platform. Running at operating speeds in excess of a gigahertz on Samsung’s 32nm low power process, the hardened core has already been deployed in the industry’s first Cortex-A15 processor-based SoC for mobile computing devices. The high speed was enabled through a unique combination of innovative optimization techniques and differentiated high-performance technologies which have made IC Compiler the tool of choice for high-performance designs across multiple process nodes.
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Atrenta Ships 4.7 Release of SpyGlass® Platform

May 1, 2012

SAN JOSE, Calif — May 1, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the availability of release 4.7 of its SpyGlass® RTL analysis and optimization platform.
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Synopsys Extends HAPS Debug Visibility by 100X

Apr 26, 2012

MOUNTAIN VIEW, Calif., April 25, 2012 – Highlights • Combination of new Synopsys HAPS hardware and Identify software enables greater visibility of internal signals in FPGA-based prototypes to accelerate SoC design debug • New release provides approximately 100X more storage capacity for signal traces with sample speeds up to 60 MHz • Utilization of FPGA memory resources significantly reduced to better accommodate complex SoC prototyping projects
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ACCO Selects Berkeley Design Automation Analog FastSPICE™ Platform for Verification of Innovative Wireless Solutions

Apr 24, 2012

SANTA CLARA, CA, — April 24 , 2012— Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that ACCO Semiconductor Inc., a fabless semiconductor company developing innovative solutions for the wireless industry, has selected the company’s Analog FastSPICE (AFS) Platform for block-level characterization and full-circuit verification of their CMOS RF designs.
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Atrenta Expands Technical Advisory Board in Europe

Apr 24, 2012

GRENOBLE, France — April 24, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the creation of a European technical advisory board (TAB). This group expands the existing Atrenta TAB, which is composed of high-profile researchers and professors in the US and Asia. The expansion of its TAB into Europe supports Atrenta’s growing R&D center there, co-located at the MINATAC innovation campus in Grenoble.
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Atrenta Offers IP Kit Spring Cleaning Promotion

Apr 16, 2012

SAN JOSE, Calif. — April 16, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, is offering semiconductor design groups access to the Atrenta IP Kit through a free 2-week trial promotion.
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STARCHIP develops a High-performance 32-bit RISC Secure core based on CORTUS APS3s CP

Apr 16, 2012

MEYREUIL, April 11th, 2012- StarChip®, experts in designing and qualifying Smart Card ICs announced today the development of the ARX (Fortress in Latin). The ARX CPU is a High-performance 32-bit RISC Secure Core based on Cortus’ APS3s CPU. This announcement is a step further to confirm StarChip®’s strategic commitment to Smart Card business by extending its product portfolio to payment and ID markets.
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Synopsys’ StarRC Extraction Solution Certified by UMC for 28-nm Designs

Apr 3, 2012

MOUNTAIN VIEW, Calif., April 3, 2012— Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that UMC has certified Synopsys’ StarRC™ parasitic extraction solution for its latest 28-nanometer (nm) process technologies. The StarRC solution delivered silicon-validated accuracy on UMC’s evaluation designs to meet the qualification criteria for its advanced 28-nm Poly SiON and High K/Metal gate processes. The StarRC technology files are immediately available to UMC customers working with its 28-nm processes.
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Latest Synplify FPGA Synthesis Software Offers New High-Reliability Features and Improves Productivity for FPGA-Based Prototyping

Apr 2, 2012

MOUNTAIN VIEW, Calif., April 2, 2012 -- Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced availability of the latest release of its Synplify Pro® and Synplify® Premier FPGA synthesis tools. The Synplify 2012.03 products include improved synthesis algorithms that accelerate runtime by up to 30 percent. In addition, the Synplify Premier software is enhanced with a new continue-on-error feature to address FPGA designers’ need for fast turnaround time by enabling them to generate a report and fix all errors resulting from missing or incorrect design definitions at the end of the hardware description language (HDL) compilation step rather than incrementally fixing an error and rerunning the compile step. This capability is especially important with SoC prototypers who may not be intimately familiar with the HDL code they have to implement in an FPGA. Additionally, the new Synplify Premier software release further automates the process of building high reliability and fault tolerance into an FPGA design using a combination of advanced features including selective triple modular redundancy (TMR), fault-tolerant error correcting code (ECC) memories and Hamming-3 encoding for detection and correction of soft errors.
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Synopsys’ Collaboration with Industry Consortium Yields Double Patterning Technology Models for Parasitic Extraction

Mar 28, 2012

MOUNTAIN VIEW, Calif., March 28, 2012— Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that its collaboration with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) has resulted in a parasitic variation modeling solution to address the effects of double patterning technology (DPT), targeted for use in 20-nanometer (nm) IC manufacturing. The new DPT model extensions will be available to the EDA and semiconductor industries through the open source licensed Interconnect Technology Format (ITF) version 2012.06 ratified by IMTAB members, including Apache Design – a subsidiary of ANSYS, GLOBALFOUNDRIES, NVIDIA, Synopsys and others (the full member list is available at www.imtab.org).
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Synopsys’ StarRC Extraction Solution Enables More Than 150 Successful 28nm Tapeouts

Mar 28, 2012

MOUNTAIN VIEW, Calif., March 28, 2012— Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that its StarRC™ parasitic extraction solution has enabled more than 150 successful 28-nanometer (nm) tapeouts, delivering fast turnaround time and the signoff accuracy required for next-generation designs across computer, consumer, mobile and wireless communications applications. StarRC’s advanced modeling of complex process effects at the 28-nm silicon process technology node and its leading qualification by major foundries provides lower design risk and improved opportunity for one-pass tapeout success. StarRC is already used by more than 40 semiconductor companies for 28-nm design signoff, confirming its position as the industry’s gold standard extraction solution through several generations of process technologies.
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Synopsys, Altera and TSMC Collaborate to Deliver Silicon-Accurate Parasitic Modeling and Extraction for 28-nm Processes

Mar 28, 2012

MOUNTAIN VIEW, Calif., March 28, 2012 — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that it collaborated with Altera and TSMC to silicon-validate modeling of key parasitic effects in Synopsys’ StarRC™ solution for TSMC’s 28-nanometer (nm) processes. The StarRC solution achieved the stringent model-to-silicon accuracy criteria of TSMC’s 28-nm process technology to enable high-performance designs at the advanced node. Altera Corporation, a pioneer in programmable logic, has successfully deployed StarRC to achieve signoff accurate extraction and accelerate the design cycle of its 28-nm FPGA designs.
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Synopsys Extends Leadership in Storage Standards Verification IP

Mar 26, 2012

MOUNTAIN VIEW, Calif., March 22, 2012 – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced availability of verification IP (VIP) for Non-Volatile Memory Express (NVMe), an emerging storage protocol for connecting solid state drives (SSDs) directly to the PCI Express® interface. With the addition of the NVM Express protocol to its leading serial ATA (SATA) and serial attached SCSI (SAS) verification IP, Synopsys expands its portfolio and leadership in verification IP for storage protocols.
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Synopsys Unveils 3D-IC Initiative

Mar 26, 2012

MOUNTAIN VIEW, Calif., March 26, 2012—Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today unveiled its initiative to accelerate the design of stacked multiple-die silicon systems using 3D-IC integration to meet the requirements of faster and smaller electronic products that consume less power. As part of its 3D-IC initiative, Synopsys is working closely with leading IC design and manufacturing companies to deliver a comprehensive EDA solution, including enhanced versions of its IC implementation and circuit simulation products.
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Synopsys Unveils Virtualizer Development Kits to Accelerate Software Development for ARM big.LITTLE Processing

Mar 21, 2012

MOUNTAIN VIEW, Calif., March 21, 2012 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the first release of the Virtualizer™ Development Kit (VDK) Family for accelerating software development. The VDK Family for ARM Cortex Processors contains multiple reference designs, analysis and debug software tools for the Cortex-A15 MPCore processor and ARM big.LITTLE processing. By using the VDKs developers can now optimize for performance and energy efficiency prior to board availability. The reference designs can easily be customized for device specific requirements using Synopsys’ Virtualizer solution.
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Synopsys and Applied Materials Collaborate on TCAD Models for Next-Generation Logic and Memory Technologies

Mar 15, 2012

MOUNTAIN VIEW, Calif. and SANTA CLARA, Calif. – March 15, 2012 – Synopsys, Inc. (NASDAQ: SNPS) and Applied Materials, Inc. (NASDAQ: AMAT) today announced a collaboration to develop technology computer-aided design (TCAD) models for next-generation semiconductor devices. The models derived from this TCAD collaboration will enable customers to speed up process development for 14-nanometer (nm) and 11-nm logic and new memory chip technologies, allowing them to lower cost and reduce time-to-market.
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Blue Pearl Software Announces Support for Synopsys Synplify Pro Design Flow

Mar 14, 2012

SANTA CLARA, California, USA. and DRESDEN, Germany –13 March 2012 -Blue Pearl Software, Inc, a provider of next generation EDA software that increases designer productivity and design quality, announced that its Blue Pearl Software Suite, for Windows and Linux operating systems, supports Synopsys’ Synplify Pro® FPGA synthesis software for VHDL and SystemVerilog designs.
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Cortus Announces Bridges for AHB-Lite™ and APB™ to Enable Migration to the APS and FPS Processor Product Range

Mar 13, 2012

Dresden, Germany, 12th March 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the release of two bridges for their processor product range. The first bridge is between the Cortus APS bus and AHB-Lite™ while the second bridge is between the APS bus and APB™.
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GUC and Synopsys Achieve Design Milestone

Mar 13, 2012

HSINCHU, TAIWAN AND MOUNTAIN VIEW, Calif., March 13, 2012 -- Global Unichip Corp. (GUC; TW:3443), the Flexible ASIC LeaderTM and Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced the tape out of 30 customer devices during the past four years using a combination of Synopsys’ DesignWare® IP and GUC’s ASIC design services.
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Cortus announces Processor IP Roadmap for Embedded System on Chip (SoC) Applications

Mar 12, 2012

Montpellier, France 21st February, 2012. Cortus S.A., a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces its plan to launch three new microcontroller IP cores as part of its processor roadmap. The new cores share common technology with the highly efficient APS3 core but address complementary market segments. The three new cores will be released over the coming six months.
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Cortus Announces FPS6 32 bit Floating Point Microcontroller IP Core for High Performance Control and Signal Processing Applications

Mar 12, 2012

Nürnberg, Germany, 28th February 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the latest member of their processor family: the high performance, high throughput FPS6 with integrated floating point. The FPS6 combines excellent integer performance, shared with the other members of the Cortus processor family, with a tightly integrated single precision floating point unit. This processor IP is designed for integration into SoCs requiring high floating point performance: for example industrial control systems, motor control, power and energy applications. The FPS6 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3.
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ClioSoft Celebrates 2011 Year-end with 53% Increase in Bookings

Mar 9, 2012

FREMONT, Calif., March 8, 2012 -- ClioSoft, Inc., developer of the premier hardware configuration management (HCM) solutions for the electronics design industry, reported a 53% annual increase in bookings for 2011. The rise in bookings was attributed to increased adoption by existing customers as well as the addition of 23 new customers. Growth in all regions was steady, with the highest growth in Europe, which booked a 139% increase over 2010. This included new enterprise deployments at Allegro Microsystems, Lattice Semiconductor, ON Semiconductor, and Rohde & Schwarz as well as significant growth at Analog Devices, International Rectifier, Linear Technology and others.
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Integrated Device Technology (IDT) Picks Silicon Frontline to Improve Power Device Reliability and Efficiency

Mar 7, 2012

Campbell, CA – March 6, 2012 – Silicon Frontline Technology, Inc. (SFT) an Electronic Design Automation (EDA) company, in the post-layout verification market, announced today that Integrated Device Technology, Inc. , the Analog and Digital Company™ delivering essential mixed-signal semiconductor solutions, is using Silicon Frontline’s R3D software for fast, resistive 3D extraction. R3D improves the reliability and efficiency of semiconductor power devices offered by IDT.
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Shanghai Huali Adoptes BSIMProPlusTM SPICE Modeling Platform for Huali’s Advanced Process Technologies

Mar 6, 2012

San Jose, California, Jan. 31, 2012 - ProPlus Design Solutions, Inc., the leader in SPICE Modeling products and technologies, today announced that Shanghai Huali Microelectronics Corporation (HLMC) has adopted its BSIMProPlusTM SPICE modeling platform and solutions to establish a complete flow, including data measurement, model parameter extraction/optimization/validation, and model retargeting for HLMC’s advanced technologies, 65/55nm, 45/40nm, and beyond.
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ProPlus Introduces NanoYield™ Integrated Circuit Design Tool: Highly-efficient design for yield (DFY) tool enabled by patented technology licensed from IBM

Mar 6, 2012

San Jose, California - October 28, 2011 ProPlus Design Solutions, Inc. (ProPlus), today announced a new product called NanoYield™, which was developed to enable highly-efficient integrated circuit yield analysis and design optimizations, and is based on patented technology licensed from IBM.
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Fujitsu Laboratories of America Adopts Berkeley Design Automation Analog FastSPICE™ Platform for High-Speed CMOS Transceivers

Mar 6, 2012

SANTA CLARA, CA, —March 6, 2012— Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that Fujitsu Laboratories of America, Inc., a wholly owned subsidiary of Fujitsu Laboratories Ltd., has selected the company’s Analog FastSPICE™ (AFS) Platform for full-circuit post-layout verification, block-level characterization, and device noise analysis of their high-speed CMOS transceiver designs.
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Calypto Adds Christopher Mausler as CFO

Mar 6, 2012

SANTA CLARA, Calif., – Mar. 6, 2012 – Calypto® Design Systems, Inc., the leader in Register Transfer Level (RTL) power optimization and Electronic System Level (ESL) hardware design, today announced that Chris Mausler has joined the company as Chief Financial Officer (CFO). Before joining Calypto, Chris was the vice president of Finance, corporate controller and acting CFO for Ubicom, Inc., a networking and multimedia semiconductor start up.
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Atrenta and TSMC IP Quality Initiative Gains Broad Industry Acceptance

Mar 5, 2012

SAN JOSE, Calif. — March 5, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that 10 intellectual property (IP) providers have qualified their soft IP for inclusion in the TSMC 9000 IP library using the Atrenta IP Handoff Kit.
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Synopsys and Arteris Develop IP Solution to Reduce Mobile Phone Memory Costs

Mar 2, 2012

MOBILE WORLD CONGRESS, BARCELONA, Spain, February 29, 2012 -- – Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, and Arteris, Inc., the inventor and leading supplier of network-on-chip (NoC) interconnect IP solutions, today announced their joint analog and digital IP solutions to implement the MIPI Alliance Low Latency Interface (LLI) 1.0 specification. The combined offerings deliver high performance with low power consumption in a compact silicon footprint while providing interoperability with the MIPI standard. By providing a collaborative solution that adheres to the LLI specification, Arteris and Synopsys give system-on-chip (SoC) designers access to pre-tested and pre-optimized analog and digital MIPI-based IP that can reduce design cost and accelerate time to market.
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Synopsys Introduces Industry’s First 28-nm Multi-Gear MIPI Alliance M-PHY IP Supporting Six Standards for Mobile Applications

Mar 2, 2012

MOBILE WORLD CONGRESS, BARCELONA, Spain, February 29, 2012 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced availability of a new DesignWare® MIPI M-PHY IP solution supporting multiple speed gears and a broad range of high-speed interfaces for mobile applications. Based on the industry’s first silicon-proven DesignWare MIPI M-PHY IP introduced by Synopsys in 2010, the new MIPI M-PHY IP is the first 28-nanometer (nm) multi-gear solution that supports six different inter-chip interconnect protocols including the JEDEC Universal Flash Storage (UFS), the USB SuperSpeed Inter-Chip (SSIC), and the MIPI Alliance’s Low Latency Interface (LLI), DigRF v4 and future CSI-3 and DSI-2 interfaces. By providing application-oriented M-PHY IP that runs at multiple speeds and is interoperable with multiple protocols, Synopsys enables design teams to “future-proof” their designs while reducing the risk and cost of integrating MIPI interfaces into basebands, application processors and mobile ICs.
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