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DAC 2013 AUSTIN, TX | JUNE 2-6

Exhibitor News


Ausdia Receives Patent for System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs

May 20, 2013

Sunnyvale, Calif. – May 20, 2013– Ausdia, the leading developer of timing constraints verification and management solutions that complement timing signoff for complex system-on-chip (SoC) designs, has been issued patent number US 8,438,517 B2 by the United States Patent and Trademark Office. The patent, which discloses automated techniques for identifying and managing the relationship between clock domains in an integrated circuit (IC) design, extends the company’s technology lead.
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SMIC Utilizes ProPlus’ NanoYield High-Sigma Solution to Optimize SRAM Yield for 28nm Process Development

May 15, 2013

SAN JOSE, CALIF. –– May 15, 2013 –– ProPlus Design Solutions, Inc. (www.proplussolutions.com) announced today that Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) has deployed ProPlus’ NanoYield™ High-Sigma (HS) within its advanced technology development flow.
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Forte Design Systems Announces Cynthesizer 5 SystemC High-Level Synthesis

May 14, 2013

SAN JOSE, CALIF. –– May 14, 2013 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software to enable design at a higher level of abstraction, today unwrapped its enhanced Cynthesizer™ SystemC-based high-level synthesis (HLS) product. The new version includes low power synthesis capabilities, core synthesis algorithms, and a new SystemC integrated development environment (IDE).
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High-Level Synthesis Software from Forte Design Systems Adopted by LG

May 14, 2013

SAN JOSE, CALIF. –– May 15, 2012 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software to enable design at a higher level of abstraction, today announced that LG Electronics (www.lg.com) of Seoul, Korea, has adopted Cynthesizer™ SystemC high-level synthesis (HLS) for its next-generation digital television (DTV) design project.
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Breker Verification Systems Celebrates 10-Year Anniversary

May 14, 2013

SAN JOSE, CALIF. –– May 14, 2013 –– Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company, will celebrate its 10th anniversary now through the 50th Design Automation Conference (DAC), where it will exhibit in Booth #2015 June 3-5 at the Austin Convention Center in Austin, Texas.
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Atrenta India Announces New R&D Facility in Noida

May 8, 2013

Noida, UP — May 8, 2013 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced its recent relocation into an expanded R&D facility at A-12 & A-29, Sector-2, Noida, UP. The new facility houses Atrenta's current staff and meets near-term growth requirements, keeping pace with the company's global expansion plan.
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Forte Design Systems Launches YouTube Channel as Part of Enhanced Education, Training Program

May 7, 2013

SAN JOSE, CALIF. –– May 7, 2013 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software to enable design at a higher level of abstraction, today launched the Forte Design Systems Channel (www.youtube.com/ForteDesignSystems) on YouTube as part of its enhanced education and training program.
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Sage Design Automation launched, with design rule compiler technology and products

May 6, 2013

Santa Clara, California - May 6, 2013 - Sage Design Automation (Sage-DA) has been founded to develop technology and products that automate the rule-based design and verification paradigm. Sage-DA was founded with initial investment from venture capital and angel investors including Alex Shubat, PhD, former President and CEO of Virage Logic (NASDAQ: VIRL, acquired by Synopsys in 2010) and Michael Burstein, PhD, EDA veteran and co-founder of multiple EDA companies. Coby Zelnik, former CEO of Sagantec, leads the company as President and CEO.
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IC Manage Releases 5th Annual Global Design Data Management Survey Results

Apr 29, 2013

CAMPBELL, Calif., Apr 24, 2013 – IC Manage, Inc. today announced the availability of its fifth annual Global Design Management Report. This year’s report is on IP Reuse – Design and Verification and covers the results of a 372 respondent survey of SOC and IC design professionals; it spans design reuse, verification reuse, and dependency management.
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IC Manage Hires Craig Shirley as Vice President of Worldwide Sales

Apr 29, 2013

CAMPBELL, Calif. April 24, 2013 – IC Manage, Inc. today announced that Craig Shirley has joined the company as vice president of worldwide sales. Mr. Shirley will lead the company’s sales organization to extend its leadership in Design and IP Management.
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Docea Power to participate to ESL & Platform session at EDPS 2013

Apr 17, 2013

What Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, announces that it will participate to the Electronic Design Process Symposium (EDPS) 2013 in Monterey, CA on April 18, 2013.
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Flexras Technologies Enhances Wasga Compiler Partitioning Tool, Adds Support for Virtex-7 FPGA-based FPGA Platforms

Apr 16, 2013

Paris, France – April 16, 2013 – Flexras Technologies, the provider of high performance partitioning software, today announced the release 3.2 of its WasgaTMCompiler Design Suite for FPGA-based prototyping. This new release supports the Xilinx® Virtex®-7 FPGA and includes new features that accelerate SoC rapid prototyping.
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frobas Chooses SpyGlass® CDC For SoC Design Flow

Apr 16, 2013

SAN JOSE, Calif — Apr 16, 2013 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced that frobas GmbH will collaborate with Atrenta on the integration of their SpyGlass® CDC clock domain crossing verification product into frobas’ advanced SoC design flow. The terms of the collaboration will be managed as part of Atrenta’s SpyLinks™ partner program.
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EDA Industry to Recognize Dr. Chenming Hu with the Phil Kaufman Award at DAC 2013

Apr 10, 2013

SAN JOSE, California – April 2 2013 – Dr. Chenming Hu, TSMC Distinguished Professor of the Graduate School at the University of California, Berkeley, has been selected by the EDA Consortium (EDAC) and the IEEE Council of EDA (CEDA) as recipient of the 2013 Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation (EDA). .
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ProPlus Design Solutions Unveils Next-Generation Pure SPICE Simulator

Apr 3, 2013

SAN JOSE, CALIF. –– April 2, 2013 –– ProPlus Design Solutions, Inc. (www.proplussolutions.com), the global leader for SPICE modeling solutions and the leading technology provider for Design-for-Yield (DFY) applications, today launched NanoSpice™, the next-generation high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation.
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Atrenta Receives Award from Second Harvest Food Bank

Apr 2, 2013

SAN JOSE, Calif — Apr 2, 2013 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, will receive the “Bumper Crop” award from the Second Harvest Food Bank at their upcoming Make Hunger History celebration. The award is in recognition of Atrenta’s substantial year-over-year increase in contributions to Second Harvest Food Bank of 51 percent and the company’s continued support of the organization’s work over the years.
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Docea Power Unveils New Release of Aceplorer and AceThermalModeler, Enables Dynamic Power and Thermal Management Analysis with Real Use Cases

Mar 14, 2013

Grenoble, France and San Jose, CA – March 14, 2013 – Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today announced new releases of Aceplorer 3.1 and AceThermalModeler 2.0.
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Carbon Expands Embedded Systems Offerings

Mar 5, 2013

ACTON, MASS. –– March 5, 2013 –– Carbon Design Systems® Inc. (www.carbondesignsystems.com) announced today that its newest Carbon Performance Analysis Kit (CPAK™) featuring the ARM® Cortex™-R7 processor is available for download from the Carbon IP Exchange web portal (www.carbonipexchange.com).
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OneSpin Solutions, Oasys Design Systems Ink OEM Agreement

Feb 26, 2013

MUNICH, GERMANY and SANTA CLARA, CALIF. –– February 26, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) and formal equivalence checking solutions, and Oasys Design Systems (www.oasys-ds.com), provider of Oasys RealTime physical register transfer level (RTL) exploration and synthesis software, today announced they have signed an original equipment manufacturer (OEM) agreement.
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Breker Verification Systems Enhances TrekSoC GUI

Feb 18, 2013

SAN JOSE, CALIF. –– February 18, 2013 –– Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company, today unveiled an enhanced graphical user interface (GUI) for TrekSoC™, software that automatically generates self-verifying and synchronized C test cases to run on an SoC’s multiple heterogeneous embedded processors for faster and more thorough verification.
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Forte Design Systems Becomes First High-Level Synthesis Software Provider

Feb 12, 2013

SAN JOSE, CALIF. –– February 12, 2012 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software products that enable design at a higher level of abstraction and improve design results, today announced its Cynthesizer™ high-level synthesis (HLS) is the first HLS software to support IEEE 1666™-2011 SystemC
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OneSpin Solutions Unveils OneSpin 360 DV Product Family

Feb 11, 2013

MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced the bundling of multiple verification tools into its new OneSpin 360™ DV Product Family.
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OneSpin Solutions Adds RTL-to-RTL Equivalence Checking to Product Family

Feb 11, 2013

MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced immediate availability of 360™ EC-RTL, equivalence checking software that compares revisions of register transfer level (RTL) code.
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Reflex CES Enters Mainstream FPGA-Prototyping Market; Offers 25-Million Gates or More ASIC Prototyping Platform with Partitioning Software

Feb 11, 2013

PARIS, France – February 11, 2013 - Reflex CES, a provider of custom embedded and complex systems, today introduced FPP25, a fast ASIC/SOC prototyping platform for emulating designs of up to 25-million ASIC gates using a stand-alone system. Based on Xilinx Virtex-7 2000T FPGAs, FPP25 exploits Reflex CES’ collaboration with Flexras, an EDA company specializing in FPGA design partitioning software, and Adacsys, a functional verification software provider, to offer design engineers an easy-to-use, next generation platform to speed up validation and verification of complex, high density digital designs.
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Calypto Announces New President and CEO Sanjiv Kaul

Feb 6, 2013

SAN JOSE, Calif., – February 4, 2013 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, today announced that Sanjiv Kaul has joined the company as President and Chief Executive Officer (CEO).
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Blue Pearl Announces North American Expansion

Dec 18, 2012

Santa Clara, California– December 18, 2012 -- Blue Pearl Software, the provider of EDA software that accelerates RTL signoff for FPGA designs, today announced it has added sales and support staff in North America due to the increased interest in using the Blue Pearl Software Suite for designs in the embedded, military and medical devices markets.
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Reflex CES Introduces Industry’s First Aurora-Like IP Core, Offers Freedom to Choose Best FPGA Technology by Enabling Interoperability between Leading FPGA Platforms

Dec 18, 2012

PARIS-EVRY-France – December 12, 2012 - Reflex CES, a provider of custom embedded and complex systems, today announced the industry’s first release of the Reflex CES Aurora-like IP Core based on Altera FPGAs. The core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs.
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Blue Pearl Software Opens Japan Office and Appoints Katsuhiko Sakano as Sales Director to Support Growing Interest in FPGA Design Tools for Embedded Applications

Dec 13, 2012

Santa Clara, California and Tokyo, Japan – December 13, 2012 -- Blue Pearl Software, the provider of EDA software that accelerates RTL signoff for FPGA designs, today announced it has opened a Japan office in Tokyo, and appointed Katsuhiko Sakano as its Director of Sales.
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Atrenta Ships 5.0 Release of SpyGlass® Platform

Dec 3, 2012

SAN JOSE, Calif — Dec 3, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today the 5.0 release of its SpyGlass® RTL analysis and optimization platform. This is also the first unified release of the SpyGlass and GenSys® platforms. The release contains extensive enhancements for performance, accuracy and usability, and many are the direct result of customer feedback.
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Atrenta Expands Sales and Support Operations in Israel

Nov 26, 2012

EVEN YEHUDA, Israel — Nov 26, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today a significant expansion in its sales and support operations in Israel with the addition of a dedicated sales manager and a customer solutions architect.
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Atrenta Number Two in RTL Power Analysis According to Gary Smith EDA

Nov 12, 2012

SAN JOSE, Calif — Nov 12, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, is the number two supplier of RTL power analysis tools according to the 2012 Market Trends Report published by Gary Smith EDA. The popular report on the EDA market shows Synopsys as the number one vendor in the segment with Atrenta leading the nearest competitor by seven percent.
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Tanner EDA Grows Revenue, Technology Partnerships and Customer Base for Fiscal 2012

Nov 9, 2012

MONROVIA, California – November 7, 2012 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), closed fiscal 2012 (year ending May 2012) with strong growth across a number of key business and technology metrics. The company celebrated its 25th year in business with growth in revenues, new customers, product offerings, technology partnerships and foundry relationships.
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Episil Selects Berkeley Design Automation AFS Nano for Analog and Power Semiconductor Devices

Nov 6, 2012

Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that Episil Technology, Inc., a pure-play foundry house specializing in epitaxial and silicon wafer foundry services for power and analog semiconductor products, has selected the company’s AFS Nano SPICE simulator for analog and power device characterization.
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Atrenta and TSMC Announce SpyGlass® IP Kit 2.0 Availability

Nov 1, 2012

SAN JOSE, Calif and HSINCHU, Taiwan, R.O.C. — Oct 31, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, with TSMC announced today the planned availability of IP Kit 2.0. Based on the SpyGlass® RTL design platform, IP Kit is a fundamental element of TSMC’s soft IP9000 Quality Assessment program that assesses the robustness and completeness of soft, or synthesizable IP. IP Kit 2.0 has undergone extensive beta testing by TSMC soft IP alliance partners: Digital Media Professionals Inc., Dolphin Integration, Sonics, Inc. and Vivante Corporation. IP Kit 2.0 will be fully supported on TSMC-Online and available to all TSMC’s soft IP alliance partners on Nov. 20, 2012.
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Blue Pearl Joins ARM® Connected Community®

Oct 24, 2012

Santa Clara, California – October 24, 2012 -- ARM® TechCon™-- Blue Pearl Software, the provider of EDA software that accelerates RTL signoff for FPGA designs, today announced it is a new member in the ARM Connected Community, the industry’s largest ecosystem of ARM technology-based products and services. As part of the ARM Connected Community, Blue Pearl gains access to a full range of resources to help it market and deploy its innovative Blue Pearl Software Suite for FPGA design to enable developers to get their ARM Powered® products to market faster.
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Blue Pearl Advances FPGA Design Automation, Announces Software Release with Enhanced Path Analysis

Oct 23, 2012

SAN JOSE, Calif. -October 19, 2012 -Blue Pearl Software, Inc., the provider of EDA software that accelerates RTL signoff for FPGA designs, today, announced that it is shipping Release 6.1 of its Blue Pearl Software Suite, for Windows and Linux operating systems. The new version includes enhancements that improve and further automate the FPGA design process, including one of its biggest design bottlenecks - critical path analysis.
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ATopTech’s Physical Design Solution Included in TSMC 20nm Reference Flow

Oct 11, 2012

SANTA CLARA, CA – October 10, 2012 - ATopTech, the leader in next generation physical design solutions, today announced that Aprisa™ and ApogeeTM, the company’s place and route solution, are included in TSMC’S 20nm Reference Flow. TSMC’S 20nm process technology delivers better performance and lower power consumption than previous generations. TSMC and ATopTech collaborated in incorporating ATopTech tools in the 20nm Reference Flow to address the increasing design challenges for 20nm.
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Atrenta to Present Soft IP Quality Standards at TSMC Event

Oct 10, 2012

San Jose, CA – Oct 10, 2012 What: Atrenta Speaker Anuj Kumar will present in the IP Track Session, titled - TSMC IP Kit V2.0 - Enhancing Soft IP Quality Standards
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Calypto PowerPro® Adopted by Core Logic for Advanced RTL Power Reduction

Oct 8, 2012

SANTA CLARA, Calif., – October 5, 2012 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power reduction, today announced that Core Logic Inc., Korea’s leading fabless semiconductor manufacturer, has adopted PowerPro® CG as their primary power optimization tool for designing their complex system-on-chip (SoC) products.
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Atrenta Takes Three of Five Top Spots in DeepChip DAC User Survey

Oct 3, 2012

SAN JOSE, Calif — Oct 3, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today that its products took three of the top five positions in the popular DeepChip DAC User Survey. The survey, conducted by John Cooley and published on the DeepChip portal, summarizes user inputs regarding the top products at DAC. This year’s survey included detailed responses from 178 EDA tool users.
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Altera Deploys IC Manage to Improve Design Management and IP Reuse

Aug 9, 2012

LOS GATOS, Calif., August 9, 2012-- IC Manage, Inc. today announced that Altera Corporation (NASDAQ: ALTR), the world’s leading provider of programmable logic devices, has signed a multi-year license agreement for the IC Manage Global Design Platform™ (GDP), including IP Central™, for use across the company’s worldwide development sites. Altera adopted IC Manage design management solutions to achieve higher IP reuse, trace bug interdependencies, and improve multi-site collaboration.
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Calypto Credits Record DAC to Launch of Catapult LP and #1 Ranking on ‘Cooley’s Must See’ List

Jul 31, 2012

SANTA CLARA, Calif., – July 31, 2012 – Calypto® Design Systems, Inc., a leader in SOC design and optimization, today announced record results for the 49th Design Automation Conference (DAC). Calypto attributes its DAC success to the recent launch of Catapult® Low-Power High-Level Synthesis (HLS), the first HLS tool to include power as a top level design constraint, and the #1 ranking of their PowerPro product family for RTL power reduction on John Cooley’s ‘Must See List for DAC 2012’ on DeepChip.com.
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Real Intent Adds to Japan Presence: Expands Office, Increases Staff to Meet Demand for Design Verification and Sign-Off Products

Jul 25, 2012

YOKOHAMA, Japan and SUNNYVALE, Calif. – July 25, 2012 - Real Intent, Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today that its Japan office, Real Intent KK, has expanded. The new offices are located at the Industry & Trade Center Building in Yokohama. The newly appointed staff includes Yasuo Torisawa, Country Manager at Real Intent KK and Kazutaka Kanda, Senior Application Engineering Manager.
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Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc.

Jun 25, 2012

SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
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Vanguard International Semiconductor Adopts Sagantec Migration Solution

Jun 5, 2012

Santa Clara, California – June 4, 2012 – Sagantec today announced that Vanguard International Semiconductor Corporation (VIS) has adopted Sagantec's process migration solution for its standard cell libraries to be able to quickly migrate its IP or modify it to accommodate customer needs.
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Atrenta Introduces Fast Lint for SpyGlass®

Jun 5, 2012

SAN FRANCISCO, Calif — June 4, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today at the 49th Design Automation Conference (DAC) the availability of a Fast Lint methodology for its SpyGlass RTL analysis and optimization platform. The new capability is part of Atrenta’s GuideWare reference methodology, and tests on a wide range of designs have shown a 4X to 9X speed improvement while still delivering accurate, low noise results.
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AMIQ Releases New Design-Oriented Features in the DVT IDE

Jun 4, 2012

June 4, 2012, San Francisco, CA – AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification, today released new design-oriented features in its Design and Verification Tools (DVT) IDE. These features enable design engineers to easily understand how a signal propagates in a design, connect two modules across the design hierarchy, and inspect and document a module structure.
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Northwest Logic Uses Blue Pearl Software’s Analyze to Maximize IP Core Quality

Jun 1, 2012

SAN JOSE, California–June 1, 2012 -Blue Pearl Software, Inc., a leading provider of EDA software which accelerates electronic design implementation, announced today that Northwest Logic, Inc., a leading provider of high-performance, easy-to-use, Intellectual Property (IP) cores, uses Blue Pearl’s Analyze to maximize the quality of its IP cores.
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APS5 32 bit Microcontroller IP Core for High Performance Embedded ASIC Designs Launched by Cortus

May 31, 2012

Montpellier, France, 31st May 2012. Cortus, a technology leader in cost effective, silicon efficient 32-bit processor IP, launches the latest member of their processor family: the high performance, high throughput APS5. The APS5 combines good integer computational performance with a high maximum clock frequency. This processor IP is designed for ASICs requiring more complex processor subsystems such as those with instruction and data caches or co-processors. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.
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Atrenta Probes SpyGlass® Value at DAC

May 31, 2012

SAN JOSE, Calif — May 30, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the addition of an interview program at the 49th Design Automation Conference (DAC) to be held June 3-7, 2012 at San Francisco’s Moscone Center. Customers, partners and investors will comment on how Atrenta’s SpyGlass® RTL analysis platform helps their business.
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ASTC and Tanner EDA Ink Partnership for EDA Development Tools and Services

May 30, 2012

MONROVIA, California – May 30, 2012–Tanner EDA, the catalyst for innovation for the design, layout, and verification of analog and mixed-signal integrated circuits (ICs), and Australian Semiconductor Technology Corporation (ASTC), providing global consulting services for semiconductors, software and systems, are collaborating to deliver analog /mixed signal ASIC design services and solutions globally.
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Blue Pearl Joins Xilinx Alliance Program, Accelerates Design Implementation

May 29, 2012

SANTA CLARA, California–May 29, 2012 -Blue Pearl Software, Inc., a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, announced that it has joined the Xilinx Alliance Program. Xilinx Inc. is the worldwide leader and developer of All Programmable devices. As a result of its Xilinx collaboration, Blue Pearl announces improved productivity for Xilinx Vivado™ Design Suite users, by reducing development time, run time and the number of design iterations.
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Calypto Leverages Core Technology to Expand Product Portfolio, Announces Catapult Low-Power High-Level Synthesis

May 29, 2012

SANTA CLARA, Calif., – May 29, 2012 – Calypto® Design Systems, Inc., a leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) low power optimization, today announced Catapult® Low-Power (LP), the industry's first production quality, high-level synthesis (HLS) tool that adds power as an optimization goal. By leveraging Calypto’s existing best in class power analysis and optimization technology, Catapult LP provides a closed loop optimization across power, performance and area (PPA) to address the challenges of power-aware design.
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Real Intent Leads in Speed, Capacity and Precision with New Releases of Ascent Lint and Meridian CDC Verification Tools; Demos Set for 49th DAC

May 29, 2012

SUNNYVALE, Calif. – May 29, 2012 - Real Intent, Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today the release of version 4.1 of its Meridian™ Clock Domain Crossing (CDC) analyzer and the release of version 1.5.1 of its Ascent™ Lint tool. These new releases provide significant advances over the 2011 versions of the software.
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Flexras Technologies Announces Breakthrough Automatic Partitioning Tool

May 29, 2012

SAN FRANCISCO, CA– Design Automation Conference (DAC) – May 29, 2012 – Flexras Technologies, an EDA company specializing in partitioning for FPGA-based prototyping, today announced Wasga Compiler, a software tool that boosts multi-FPGA design performance. Wasga Compiler is unique and is the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. It typically delivers a 10X clock frequency increase, runs blazingly fast, handles multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board, whether it’s off-the-shelf or custom.
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Silicon Frontline Adds New Capabilities; Focuses on Semiconductor Power Device Reliability and Efficiency, Accurate 3D Parasitic Extraction, Point-to-Point Resistance

May 25, 2012

Campbell, CA – May 24, 2012 – Silicon Frontline Technology, Inc. (SFT) an Electronic Design Automation (EDA) company, in the 3D parasitic extraction and analysis software market, announced new versions of its flagship products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures, and a new product P2P (Pont-to-Point) for IR drop analysis.
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Cortus Launches APS3R 32 bit Microcontroller IP Core for Low Energy Embedded Applications

May 24, 2012

Montpellier, France, 22nd May 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the release of the latest member of their processor family: the energy efficient APS3R. The APS3R builds on experience with the earlier APS3 core but delivers improved computational performance. For more demanding embedded applications a dual core configuration is possible.
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MOSIS to offer highly efficient Cortus APS3R microcontroller core to System on Chip (SoC) designers

May 24, 2012

Montpellier, France and Marina del Rey, California, 24th May 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP and MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, announced the signing of a sales representative agreement. Under the agreement, MOSIS will offer the Cortus APS3R and associated peripherals to their customers. The deal will support the licensing of Cortus IP from design through prototyping to volume production with MOSIS.
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APACHE DESIGN RELEASES FOURTH-GENERATION REDHAWK FOR SUB-20 NANOMETER POWER SIGN-OFF

May 23, 2012

Pittsburgh – May 1, 2012 – ANSYS (NASDAQ: ANSS) subsidiary Apache Design, Inc. today introduced RedHawk™-3DX to meet the power, performance and price demands of low-power mobile, high-performance computing, consumer and automotive electronics. This fourth-generation power sign-off solution delivers greater accuracy, capacity and usability for full-chip dynamic power and reliability simulation to manage power consumption and improve power delivery efficiency of advanced integrated circuit (IC) designs.
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Pulsic to Introduce Place and Route Implementation Solution for Analog and Custom Digital Design at DAC 2012

May 22, 2012

SAN JOSE, CALIF., May 22, 2012 -- Following up on the Pulsic Planning Solution™ products introduced last year at DAC, Pulsic, the premier provider of physical design tools for precision design automation, will introduce a place-and-route implementation solution at DAC 2012 in San Francisco. The Pulsic Implementation Solution™ builds on the work of the planning tools, providing designers with easy-to-use, guided flows to automatically implement precise, hand-crafted quality design layouts with the highest routing completion and accuracy on the market.
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Docea Ships New Version of Power and Thermal Analysis Software,

May 22, 2012

SAN FRANCISCO, CA--Design Automation Conference (DAC) --May 22, 2012 - Docea Power, the design-for-low-power company that delivers Electronic System Level (ESL) software tools for power and thermal analysis and modelling, announced that it is shipping Aceplorer™ 3.0 with an event scheduler for enhanced scenario creation capabilities and support for thermal models generated by its AceThermalModeler for coupled power and thermal simulations capabilities. In addition, it is announcing AceThermalModeler™ 1.1 with an enhanced 3D viewer for fast model debugging.
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Real Intent’s Focus on Excellent Tools for Early Functional Verification & Advanced Sign-Off for Circuit Design Results in Over 35% Revenue Growth in First Half of 2012

May 22, 2012

Sunnyvale, California – May 21, 2012 –Real Intent Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today that that the company’s revenue in the first half of fiscal 2012 increased more than 35% when compared to the last half of fiscal 2011 and the company is on track to have an annual growth of over 100% by the end of 2012. In addition, the company’s customer list grew by over 30%, adding major semiconductor companies in storage, computing, networking, communications and consumer electronics industries.
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Etron Selects Berkeley Design Automation Analog FastSPICE™ Platform

May 21, 2012

SANTA CLARA, CA, —May 22, 2012— Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that Etron Technology, Inc., a world-class fabless IC design and product company specializing in specialty memory and system chips, has selected the company’s Analog FastSPICE™ (AFS) Platform for characterization and verification of their memory designs for low-power and consumer applications.
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