APS5 32 bit Microcontroller IP Core for High Performance Embedded ASIC Designs Launched by Cortus
May 31, 2012
Montpellier, France, 31st May 2012. Cortus, a technology leader in cost effective, silicon efficient 32-bit processor IP, launches the latest member of their processor family: the high performance, high throughput APS5. The APS5 combines good integer computational performance with a high maximum clock frequency. This processor IP is designed for ASICs requiring more complex processor subsystems such as those with instruction and data caches or co-processors. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.
(*CoreMark 1.0 : 1.931468 / GCC4.5.3 20120201 (Cortus Eval) -mmul -flto -O3 -funroll-all-loops -finline-limit=500 -IC:/cortus-ide/toolchain/aps3/include -DPERFORMANCE_RUN=1)
The Cortus APS5 is a high performance, high throughput, 32-bit processor designed for complex embedded systems and features a high performance integer unit and an instruction cache. It is the third member of the Cortus microcontroller IP core family to be released in 2012 complementing the smaller energy efficient APS3R and the larger floating point FPS6.
“The APS5 delivers very good computational performance and scalability making it suitable for more complex embedded subsystems”, said Michael Chapman, CEO and President of Cortus. He adds, “Despite its modest CPU core area, the APS5 delivers 2.29 DMIPS/MHz”. In common with other Cortus processors, the APS5 has a 5 to 7 stage integer pipeline and out-of-order completion ensuring that most integer instructions (load and stores included) are executed in a single cycle. Michael Chapman explains, “The APS5 architecture enables a high maximum clock frequency, for example it is capable of greater than 400 MHz in a 90 nm technology”.
The APS5 has been designed to provide scalable computing performance and is supplied with an instruction cache and a data cache is optional. Performance can be increased with symmetric multi-processing (SMP) configurations such as dual- or quad-core. For example, while a single APS5 core offers 1.93 CoreMarks/MHz* a dual-core configuration benchmarks at 3.51 CoreMarks/MHz. For SMP configurations a coherent data cache with snoopy protocol is available. Other applications may benefit from heterogeneous APS5/APS3R configurations.
The modest APS5 CPU core silicon footprint of 0.088 mm2 in 90 nm (UMC) and the freely available complete toolchain and IDE ensure a very low cost of ownership for APS5 licensees. The easy software development, programming in high level languages, with simple debugging due to an integrated debugger and simulator enhance both time to market and software reliability.
As a member of the Cortus family of processors, APS5 interfaces to all of Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. It also shares the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead. Bridges to and from AHB-Lite™ and to APB™ ensure easy interfacing to other IP.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium μC/OS and μCLinux.
AHB, AHB-Lite and APB are trademarks of ARM Limited.
About Cortus S.A.:
Cortus is exhibiting at the Design Automation Conference (DAC) 2012 in San Francisco, California from 4th-6th June at Booth #304.
Cortus S.A. is the cost/performance leader for 32 bit processor IP for embedded systems. Cortus cores are used in applications where one or more of small silicon footprint, low power consumption, good code density/small code memory size and high performance are important.
Cortus is the world leader in terms of DMIPS per square micrometre and DMIPS per microwatt.
Cortus S.A. Contact:
David Kerr-Munslow, +184.108.40.206.70.00