AMIQ Releases New Design-Oriented Features in the DVT IDE
Jun 4, 2012
June 4, 2012, San Francisco, CA – AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification, today released new design-oriented features in its Design and Verification Tools (DVT) IDE. These features enable design engineers to easily understand how a signal propagates in a design, connect two modules across the design hierarchy, and inspect and document a module structure.
The DVT IDE is a powerful and complete code development environment for the e language SystemVerilog, Verilog and VHDL. It increases the speed and quality of code development and simplifies the maintenance of reusable libraries and legacy code. DVT is built on the Eclipse Platform and comprises an IEEE standard-compliant parser, a smart code editor, and a complete suite of tools that help with code readability, navigation, task tracking, documentation, and debugging. The DVT IDE integrates with all major simulators, revision control systems, and bug tracking engines. It also supports the popular verification methodologies UVM, OVM, and VMM.
The Design and Verification Tools IDE has been created from the beginning, as its name shows, with both design and verification in mind. Although DVT’s early adopters were verification engineers, its popularity has rapidly increased among design engineers. The capabilities released today are the result of listening to the designers’ feedback and requests.
The first of the newly released features – Trace Port Connections – allows users to understand how a signal propagates in a design. The signal that needs to be traced is highlighted in the design hierarchy tree in the Trace Connections View. Users can easily locate the signal source, operation called “trace drive”, or the signal destination, operation called “trace load”.
The second new capability – Connect Module Instances – helps connect two modules across the design hierarchy. Such an operation can be tedious and error prone. With DVT, adding all the required ports from the source (output) module to the destination (input) module across the design hierarchy becomes straightforward. Before performing the operation, a user can preview both the design structural changes and source code changes.
A third capability – Module Diagrams – is similar to the DVT’s popular UML diagrams, which allows verification engineers to inspect classes. Module Diagrams allows designers to inspect and document the structure of a module, by showing a module's direct submodules, the connections between them, and the connections to the module's ports. The diagrams are always synchronized and directly linked with the source code.
For further information about these new capabilities, please visit the “What’s New” section of the DVT website: www.dvteclipse.com/help.html?documentation/sv/whatsnew.html.
AMIQ EDA is exhibiting at the 49th edition of DAC on June 4-6, 2012, in San Francisco. The show’s visitors can see a demonstration of the new features by visiting AMIQ at Booth #1804.
About AMIQ EDA
AMIQ EDA focuses on adding value to the design and verification domains through its proprietary code development and analysis tools. Since 2006, its Design and Verification Tools (DVT) platform, the first IDE for e, SystemVerilog, and VHDL, has helped engineers increase the speed and quality of code development, enabling them to complete their projects faster. Its newer product, Verissimo SystemVerilog Testbench Linter, allows verification groups to improve testbench code reliability and functionality as well as implement best coding practices and their own specific guidelines.