Calypto PowerPro® Adopted by Core Logic for Advanced RTL Power Reduction
Oct 8, 2012
SANTA CLARA, Calif., – October 5, 2012 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power reduction, today announced that Core Logic Inc., Korea’s leading fabless semiconductor manufacturer, has adopted PowerPro® CG as their primary power optimization tool for designing their complex system-on-chip (SoC) products.
Core Logic develops competitive SoC products and various platforms for mobile, home and automotive applications. Choosing Calypto’s PowerPro CG tool was an easy decision for them because PowerPro CG delivered the automation and quality of results that garnered 30% savings in overall project time. The savings in project time helps them remain competitive while delivering exceptional value to their customers.
“We are very proud that Core Logic chose PowerPro as the best tool on the market for reducing power in new and legacy RTL designs," said Shawn McCloud, Vice President of Marketing at Calypto, “because PowerPro has both automatic and guided use modes, it’s the only platform capable of reducing power across the entire SoC thereby cutting both overall project schedule and end product power consumption.”
PowerPro CG automates RTL power optimization
Based on Calypto’s patented sequential analysis technology, PowerPro CG reduces power by up to 60% with little or no impact on timing or area. PowerPro CG reads in an RTL design and evaluates circuit behavior across multiple clock cycles to identify sequential clock gating enable conditions. PowerPro CG then generates new low-power RTL that looks identical to the original RTL with the addition of sequential clock gating logic.
The PowerPro CG-generated RTL is comprehensively verified with Calypto’s SLEC® Pro. SLEC Pro is a sequential logic equivalence checking tool that guarantees functional equivalence between the PowerPro CG-generated RTL and the original RTL. No other solution provides this combination of automatic RTL power optimization and formal verification.
About Calypto’s Products
Catapult® high-level synthesis, SLEC (sequential logic equivalence checking) and PowerPro platforms are used to design, verify and optimize complex ASIC and FPGA designs by seven out of the top ten semiconductor companies and by over 100 leading consumer electronics companies worldwide. Calypto’s products enable engineers to dramatically improve design quality and reduce power consumption of SoCs while significantly reducing overall design and verification time.
Calypto Design Systems, Inc. is the leader in ESL hardware design and RTL power optimization.
Customers include Fortune 500 companies worldwide. Calypto is a member of the ARM Connected Community, Cadence Connections™ program, the IEEE‐SA, Synopsys SystemVerilog Catalyst Program, the Mentor Graphics OpenDoor program, and Si2 and is an active participant in the Power Forward Initiative. Calypto has offices in Europe, India, Japan and North America.
# # #
Calypto, Catapult, SLEC and PowerPro are registered trademarks of Calypto Design Systems, Inc. All other trademarks are property of their respective owners.
Note to Editors:
For a Korean version of this announcement, please contact firstname.lastname@example.org
Linda Marchant, Cayenne Communication, 919-451-0776, email@example.com