Ausdia Receives Patent for System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs
May 20, 2013
Sunnyvale, Calif. – May 20, 2013– Ausdia, the leading developer of timing constraints verification and management solutions that complement timing signoff for complex system-on-chip (SoC) designs, has been issued patent number US 8,438,517 B2 by the United States Patent and Trademark Office. The patent, which discloses automated techniques for identifying and managing the relationship between clock domains in an integrated circuit (IC) design, extends the company’s technology lead.
“Timing closure is increasingly failing or taking too long, and the timing constraint problems are usually realized so late in the design process that they have a severe impact on tape-out schedules,” said Sam Appleton, president and CEO of Ausdia. “This patent is one of the cornerstones of the technology behind our innovative timing constraint development platform, Timevision, which represents a new way for SoC and IC developers to massively increase productivity and improve results for complex designs.”
Timevision is a comprehensive timing constraints development, verification and management solution that complements implementation and timing signoff flows. Introduced at DAC 2012, Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run. Timevision helps designers create good SDC/TCL constraints and is a verification platform for existing timing constraints.
Ausdia will be exhibiting Timevision in Booth # 633 at DAC 2013 in Austin, Texas, from June 3rd to June 5th. Visit http://www.ausdia.com/dac_register.php to sign up for a personal meeting or demonstration.
Ausdia delivers standout timing constraint development, verification, and management solutions that complement all implementation and timing signoff flows. The company’s groundbreaking methodology and products give system-on-chip (SoC) and integrated circuit (IC) developers a new way to work, enabling massive productivity gains throughout the design flow. Founded in 2006, the privately-held company is headquartered in Sunnyvale, California.
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Michelle Clancy, Cayenne Communication LLC , 252-940-0981, email@example.com