Atrenta CEO Dr. Ajoy Bose to Present Keynote Address at SemIsrael Expo 2013 Conference
Nov 4, 2013
San Jose, CA – November 12, 2013
Design Methodology and its Impact on the Future of Microelectronics
Date: Monday, November 18, 2013
Time: 9:35 a.m. – 9:55 a.m.
Location: SemIsrael Expo 2013, Avenue Convention Center, Airport City, Israel.
Dr. Ajoy Bose – Chairman, President and CEO, Atrenta Inc.
We are witnessing a historic shift in the microelectronics industry. Enterprise deployment is being replaced by consumer deployment, and the semiconductor content of all products, from the most sophisticated to the mundane, is increasing at a dramatic rate.
Today’s semiconductor devices are typically called system-on-chip (SoC) designs, due to their extreme complexity. These SoC devices are changing the way we live and work. While there is great excitement around these new applications, their success depends on balancing two very strong but opposing forces.
On the one hand, consumers expect new product introductions very quickly and at lower and lower prices. On the other, SoC devices are taking longer to design due to their complexity and the cost of fabricating them in advanced process nodes is on the rise. Balancing these forces will be critical to the future growth of the microelectronics industry.
In this thought-provoking presentation, Dr. Ajoy Bose will explore these trends and examine the challenges they present. He will discuss approaches to address the substantial challenges facing the microelectronics industry using advanced design tools and new design methods.
Details about the conference track:
Atrenta will also present An Objective Quality Validation System for Soft IP and A Comprehensive Approach to RTL Signoff during the conference track as well as exhibit at the conference (Booth #28).
Atrenta’s SpyGlass Predictive Analyzer® significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScope™ verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
For more information, contact:
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This media advisory contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this media advisory.