Displaying results 1-10 (of 20)
There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation. Formal verification, on the other hand, establishes the condition under which a timing path exists based on the propagation requirements for the path. Structural analysis is fast because it is simple. Formal verification, however, is more complete and less noisy. Formal verification allows engineers to guarantee that their design is safe from silicon issues that result from an incorrect constraint specification. Structural analysis cannot make this claim because it cannot independently establish the correctness of a variety of design constraints.
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Darron May
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Oct 20, 2011
With the sheer volumes of data that are produced from today’s verification environments there is a real need for solutions that deliver both the highest capacities along with the performance to enable the data to be accessed and analyzed in a timely manner. There is no one single coverage metric that can be used to measure functional verification completeness and today’s complex systems demand multiple verification methods. This means there is a requirement not only to unify different coverage metrics’ but also to unify data from multiple tools and verification engines. Data management forms the foundation of any verification environment.
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Darron May
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Oct 13, 2011
An effective verification management system requires technology to manage the process, tools and data. Such a system should be anchored in the verification plan, which in turn is closely linked to the design specification. And the verification management tool should enable electronic closure of the verification plan by providing tools that both reduce the volume of data and give deeper visibility and control. Questa's verification management delivers all this in an environment that is modular, flexible and open. But perhaps its most attractive feature is that its various capabilities are assembled with one overarching goal in mind: to give IC design teams the best chance of producing silicon right the first time.
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Guido Sandmann, Joachim Schlosser
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Oct 11, 2011
Model-Based Design lets engineering teams verify requirements and designs early, before implementation and test, using executable specifications, multi¬domain simulations, and virtual testbeds. On a typical embedded software project, a large commercial vehicle manufacturer using Model-Based Design can realize total cost savings of more than 60% compared to traditional development. The vast majority of the savings are due to efficiencies gained in the requirements and testing phases through early verification. As the complexity of embedded systems grows, so do the costs of traditional development. In contrast, as an orga¬nization gains more experience with Model-Based Design, development costs are held in check—or even reduced—through shorter development cycles, increased reuse, and improved quality.
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Ran Avinun
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Jun 12, 2011
Hardware/software development platforms such as virtual prototyping, acceleration/emulation, and FPGA prototyping are typically provided as fragmented and isolated point tools. This paper shows how a continuum of open, connected, and scalable platforms can greatly reduce system integration and bring-up times for application-ready, hardware/software systems.
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Andreas Veneris
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Jun 6, 2011
Many recent independent surveys confirm that RTL debug takes as much as one third of the total design process. This means that verification engineers spend one third of their time understanding why failures occur, finding their root cause and fixing these problems. This bottleneck is caused by a variety of reasons, including design and verification complexity, but also because debugging tools have not evolved at the same pace as the complexity of the problem has increased in the past decade. Vennsa Technologies, supplier of automated functional verification debugging and error localization software, outlines the problem and explains ways it could be eliminated.
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Theo Drane, George Constantinides
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May 25, 2011
The formal verification of datapath continues to prove a challenge to design and verification engineers. The majority of formal verification relies on algorithms operating at the bit level, whereas high level datapath optimizations are performed at a word level. This article shows how this disparity can be overcome by the application of recent research in the area of polynomial datapath. We step through a practical procedure, which can be applied directly to RTL code as a preprocessing step before formal verification tools are invoked. The procedure leads to orders of magnitude improvements in the execution time for commonly occurring problems in datapath verification.
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Lauro Rizzatti
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Mar 23, 2011
The software team budget for an SoC is now larger than the hardware team budget. Even with half of the budget allocated to verification, over half of embedded projects fall months behind schedule. The new generation of fast emulators is one way to get this problem under control.
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Peter Marwedel
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Nov 3, 2010
This article presents a brief overview of key topics for research and development in embedded systems. Following a hypothetical design flow, special characteristics of embedded/cyber-physical systems with respect to specification techniques and modeling, embedded hardware, standard software, evaluation and validation, mapping of applications to execution platforms, optimizations and testing are presented. Links to more detailed information are provided.
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Vishnu Vimjam, Al Joseph
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Jun 8, 2010
Emerging systems have three dimensions of complexity when it comes to making them safe with respect to clock domain crossings (CDCs). First, the number of asynchronous clock domains can range from several tens to well over a hundred for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clock frequencies to be greater than 10. Third, the clock frequencies themselves can change dynamically during the course of operation of the chip (for example, when switched from one mode to another to save power). As a result, CDC verification becomes critical to ensure that metastability is not introduced into the design. In this article, we describe several situations and provide examples to showcase challenges in CDC verification.
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