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Embedded System Design
System-Level (Co-)Design
Verification
Challenges in Verification of Clock Domain Crossings
Tuesday, June 8, 2010
By:
Vishnu Vimjam
/ Real Intent Inc.
,
Al Joseph
/ Real Intent Inc.
Topic:
Front-End —
Sub-topic
: Verification
Summary
Emerging systems have three dimensions of complexity when it comes to making them safe with respect to clock domain crossings (CDCs). First, the number of asynchronous clock domains can range from several tens to well over a hundred for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clock frequencies to be greater than 10. Third, the clock frequencies themselves can change dynamically during the course of operation of the chip (for example, when switched from one mode to another to save power). As a result, CDC verification becomes critical to ensure that metastability is not introduced into the design. In this article, we describe several situations and provide examples to showcase challenges in CDC verification.
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