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Debug Limited No More: The Case for Debug Automation

Monday, June 6, 2011
By: Andreas Veneris / Vennsa Technologies
Topic: Front-End — Sub-topic: No Topic

Summary

Many recent independent surveys confirm that RTL debug takes as much as one third of the total design process. This means that verification engineers spend one third of their time understanding why failures occur, finding their root cause and fixing these problems. This bottleneck is caused by a variety of reasons, including design and verification complexity, but also because debugging tools have not evolved at the same pace as the complexity of the problem has increased in the past decade. Vennsa Technologies, supplier of automated functional verification debugging and error localization software, outlines the problem and explains ways it could be eliminated.

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