Displaying results 1-10 (of 25)
With today’s globalization, it’s becoming the norm for something to be invented in North America, Europe, or Japan, transferred to Taiwan or India for finalization, and then shipped to China for manufacturing. This trend has put a particular burden on the custom design process, as design quality is based on precise communication at every step. One small misinterpretation at any point can lead to an expensive design respin or—even worse—not making it to the finish line in time to win a contract.
There’s a recognized need to facilitate better communication during the long custom-design cycles. From a software point of view, design tools must help engineers maintain design “intent” throughout the entire process—whether the design is moved across the room or across the planet. From an underlying-infrastructure perspective, a remote and mobile workforce needs secure, high-performance remote access to design tools in centralized application centers. Such a workforce also must be able to share information and collaborate in real time over any network.
[read more]
Debashis De, James Johnston
/
May 23, 2011
Verific Design Automation created a Perl interface for its (System)Verilog and VHDL parsers, analyzers and elaborators. Most of its 2,000 or so APIs translated using the Simplified Wrapper and Interface Generator (SWIG), but others didn’t. This paper goes into more detail on the experience.
[read more]
Linh Hong
/
May 16, 2011
: The increasing complexity of system on chip (SoC) designs being implemented in process geometries 40nm and below is creating demand for multi-time programmable (MTP) embedded non-volatile memory (eNVM) to replace embedded read-only memory (ROM) and external flash memory. NVM based on floating-gate technology, flash memory and some forms of EEPROM (MTP) cannot be implemented in process geometries below 90nm. The ROM supplied by foundries is undesirable because of security concerns, inability to migrate to other foundries, and large area for memories density above four kilobits (4kb). A new MTP NVM solution that leverages anti-fuse technology addresses both shortcomings and provides solutions to a number of high-volume consumer and mobile applications. Other benefits include cost reduction, improved performance, enabling secure storage and configurability. This paper detail embedded NVM technologies and applications that benefit most from using embedded NVM
[read more]
Angan Das
/
May 12, 2011
Lack of adequate analog automation in today’s era is a primary factor for high turn-around-time of design spin-offs. CAD engineers need to provide better and converged analog CAD tools and solutions to meet the rising demands of the design engineer. Amongst other tasks, analog IP (AIP) characterization is an important requirement of several microprocessor design teams. It enables the creation of black-box models for AIPs, which may be fed to higher-level analysis tools. Towards this end, most of the flows till date have been manual and ad-hoc in nature. This paper introduces ACTER – a new tool for automated analog IP characterization. ACTER encompasses timing and power characterizations, with capability for individual characterization conditions, if required. The tool also computes block and pin attributes for the AIP. ACTER drives convergence efforts, introduces an easier support model, and has limited GUI capabilities, amongst other advantages. This work is a genuine effort towards a central standardized tool to consolidate collateral generation for AIPs. Presently it has been productized among several microprocessor design teams at Intel Corporation and a positive impact has been observed till now.
[read more]
Mike Hutton
/
May 6, 2011
Increasing ASIC development cost has pushed more and more designs into programmable logic and FPGAs, once restricted to prototype and glue logic, experienced 50% growth in 2010. This article gives an overview of the underlying architecture of FPGAs, recent trends in commercial offerings, and some of the research topics around FPGAs, along with discussion of the new application domains for programmable hardware.
[read more]
Endric Schubert, Glen Steiner
/
Feb 28, 2011
This paper describes design choices for closed-loop Real- Time Control Systems, a special kind of Cyber-Physical Systems, to overcome the challenges of managing time and concurrency in the computational part. An practical and proven approach is discussed which segregates the timing and concurrency aspects of the real-time control from a) the interfaces to the physical world and b) the user application software.
[read more]
Michel Tabusse
/
Feb 23, 2011
Better than Excel sheets, configurable and automated dashboards help both hardware designers and design management monitor and improve design quality. Rather than use a home-grown, script-based system or a commercial system that requires a change in methodology, configurable dashboards can track and check the myriad of people and project pieces for development of IP, SoC, software drivers, full products, etc. This article highlights the most important issues to address and links to more in-depth articles.
[read more]
Laura Lowell
/
Oct 26, 2010
A lot of marketers think tradeshows are dead. Yet, seventy-two percent of US manufacturers plan to invest in Tradeshows/Events, according to MarketingSherpa’s Business Technology Benchmark Guide 2006.9 Now that almost everything can be done online or virtually, it is easy to assume that the tried and true industry tradeshows are less important.
[read more]
Editors, DAC.com Knowledge Center
/
Jun 8, 2010
Ajith Amerasekera is Director of Texas Instruments’ Kilby Labs in Dallas, Texas. He joined Texas Instruments in 1991 and is a TI Fellow. His Ph.D. is in Electrical Engineering and Physics. He previously served as CTO for TI’s application-specific integrated circuit division, and is the holder of 28 issued patents and the author of four books on semiconductors. In this interview, Dr. Amerasekera discusses his role at TI and future research focus areas.
[read more]
Editors, DAC.com Knowledge Center
/
Jun 8, 2010
Gary Smith is founder and Chief Analyst for Gary Smith EDA. Previously, he was the Managing Vice President and Chief Analyst of the Electronic Design Automation Service, Design & Engineering Cluster at Gartner Dataquest. He is editorial chair of the IEEE Design Automation Technical Committee (DATC) and a past General Chair of the IEEE Electronic Design Processes workshop. In 2007, he received an ACM SIGDA Distinguished Service award. In this interview, Gary gives insights into his background as methodologist and analyst, as well as his thoughts on what the future holds for the EDA industry.
[read more]
All Knowledge Center Offerings