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SystemVerilog Made Easy: A Perl Interface to a Full IEEE 1800 Compliant Parser

Monday, May 23, 2011
By: Debashis De / Verific Design Automation,
James Johnston / Verific Design Automation
Topic: General — Sub-topic: No Topic

Summary

Verific Design Automation created a Perl interface for its (System)Verilog and VHDL parsers, analyzers and elaborators. Most of its 2,000 or so APIs translated using the Simplified Wrapper and Interface Generator (SWIG), but others didn’t. This paper goes into more detail on the experience.

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