Track 2, Part I - SystemVerilog Verification: Hardcore SystemVerilog for Class-Based Verification
Thursday, June 6, 2013
Time: 9:00 AM — 12:30 PM
Verification and simulation
|Organizer: ||Lori Sanine - Doulos, San Jose, CA|
|Speaker: ||John Aynsley - Doulos, Ringwood, United Kingdom|
(Includes a 30-minute coffee break)
This session will teach the hardcore object-oriented programming constructs of SystemVerilog as used by methodologies such as UVM. This session is aimed at engineers who have already had some exposure to the SystemVerilog language but are less familiar with object-oriented programming and constrained random verification, and will be a great preparation for the afternoon session on UVM.
Topics to be taught include classes, objects and inheritance, virtual interfaces, functional coverage, randomization and constraints, and more particularly how to use these language features to build a constrained random verification environment that includes a component hierarchy and transaction-level communication.
This track is taught by Doulos CTO John Aynsley, winner of the Accellera Systems Initiative 2012 Technical Excellence Award for his contribution to the development of language standards.