Track 3, Part I - ARM Accredited Engineer Program: Kick Start to the ARM (®) Cortex (TM) Family of Processors
Thursday, June 6, 2013
Time: 9:00 AM — 12:30 PM
Embedded Architecture & Platforms
|Organizer: ||Lori Sanine - Doulos, San Jose, CA|
|Speakers: ||David Cabanis - Doulos, Ringwood, United Kingdom|
| ||Kevin Welton - ARM, Inc., Austin, TX|
(Includes a 30-minute coffee break)
This session will introduce the three CPU architecture variations found in the ARM (®) Cortex (TM) Family, highlighting common traits and fundamental differences, and will be of interest to hardware engineers, software engineers and system architects wishing to learn more about ARM processor architecture. This session will discuss the programmers' model, exceptions, memory models and cache architecture and will look at system aspects such as multi-processing with an emphasis on cache coherency issues and interrupt distribution schemes.
The two sessions in this track follow the syllabus of the ARM Accredited Engineer Program
, so will be of particular interest to anyone wishing to work toward the AAE exam.
This track will be taught by ARM-approved instructors from ARM and from Doulos.