Displaying results 1-10 (of 71)
Man’s ability to create and innovate has driven society and industry throughout history. The rapid pace of change in electronics demands that we constantly evolve and innovate to enable new and wondrous products. This creative drive is showcased each year at DAC, when the most brilliant, talented and experienced minds gathers.
But no matter how much talent we have, it’s still a challenge to peer into the future and see what products, technologies and trends will be overwhelming us in the coming years. Not an easy task. However, we can unearth some hints of what lies ahead in the next 10 to 20 years by examining some of these global megatrends:
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Ajay Daga
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Apr 11, 2012
There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation. Formal verification, on the other hand, establishes the condition under which a timing path exists based on the propagation requirements for the path. Structural analysis is fast because it is simple. Formal verification, however, is more complete and less noisy. Formal verification allows engineers to guarantee that their design is safe from silicon issues that result from an incorrect constraint specification. Structural analysis cannot make this claim because it cannot independently establish the correctness of a variety of design constraints.
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Steve Lewis, Birgit Neil
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Oct 31, 2011
With today’s globalization, it’s becoming the norm for something to be invented in North America, Europe, or Japan, transferred to Taiwan or India for finalization, and then shipped to China for manufacturing. This trend has put a particular burden on the custom design process, as design quality is based on precise communication at every step. One small misinterpretation at any point can lead to an expensive design respin or—even worse—not making it to the finish line in time to win a contract.
There’s a recognized need to facilitate better communication during the long custom-design cycles. From a software point of view, design tools must help engineers maintain design “intent” throughout the entire process—whether the design is moved across the room or across the planet. From an underlying-infrastructure perspective, a remote and mobile workforce needs secure, high-performance remote access to design tools in centralized application centers. Such a workforce also must be able to share information and collaborate in real time over any network.
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Darron May
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Oct 20, 2011
With the sheer volumes of data that are produced from today’s verification environments there is a real need for solutions that deliver both the highest capacities along with the performance to enable the data to be accessed and analyzed in a timely manner. There is no one single coverage metric that can be used to measure functional verification completeness and today’s complex systems demand multiple verification methods. This means there is a requirement not only to unify different coverage metrics’ but also to unify data from multiple tools and verification engines. Data management forms the foundation of any verification environment.
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Graham Bell
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Oct 19, 2011
Geographically diverse design teams obviously face a number of challenges in the creation and verification of the IPs that form a functioning system-on-chip (SOC). Design teams often grow organically and have local versions of design tools, with the related licensing and operating systems to support these tools, and means to check-in and out those designs with other teams. Design datasets require version control of their source files, and verification sign-off steps must occur at each stage of the design process. Questions naturally arise whether design IP has been verified using the correct application and technology libraries?
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Darron May
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Oct 13, 2011
An effective verification management system requires technology to manage the process, tools and data. Such a system should be anchored in the verification plan, which in turn is closely linked to the design specification. And the verification management tool should enable electronic closure of the verification plan by providing tools that both reduce the volume of data and give deeper visibility and control. Questa's verification management delivers all this in an environment that is modular, flexible and open. But perhaps its most attractive feature is that its various capabilities are assembled with one overarching goal in mind: to give IC design teams the best chance of producing silicon right the first time.
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Guido Sandmann, Joachim Schlosser
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Oct 11, 2011
Model-Based Design lets engineering teams verify requirements and designs early, before implementation and test, using executable specifications, multi¬domain simulations, and virtual testbeds. On a typical embedded software project, a large commercial vehicle manufacturer using Model-Based Design can realize total cost savings of more than 60% compared to traditional development. The vast majority of the savings are due to efficiencies gained in the requirements and testing phases through early verification. As the complexity of embedded systems grows, so do the costs of traditional development. In contrast, as an orga¬nization gains more experience with Model-Based Design, development costs are held in check—or even reduced—through shorter development cycles, increased reuse, and improved quality.
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Karen Chow
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Jul 19, 2011
For sensitive mixed-signal designs at small process nodes, the influence of parasitic elements is growing with the increasing interactions among devices and interconnects that are in close proximity. Circuits are highly sensitive to these parasitic effects, and accurate parasitic extraction is critical for first silicon success. New 3D parasitic extraction technology applied to a flash ADC circuit design reduces the need for extra guardbanding and ensures that it will work according to the specifications when manufactured.
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Ran Avinun
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Jun 12, 2011
Hardware/software development platforms such as virtual prototyping, acceleration/emulation, and FPGA prototyping are typically provided as fragmented and isolated point tools. This paper shows how a continuum of open, connected, and scalable platforms can greatly reduce system integration and bring-up times for application-ready, hardware/software systems.
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Andreas Veneris
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Jun 6, 2011
Many recent independent surveys confirm that RTL debug takes as much as one third of the total design process. This means that verification engineers spend one third of their time understanding why failures occur, finding their root cause and fixing these problems. This bottleneck is caused by a variety of reasons, including design and verification complexity, but also because debugging tools have not evolved at the same pace as the complexity of the problem has increased in the past decade. Vennsa Technologies, supplier of automated functional verification debugging and error localization software, outlines the problem and explains ways it could be eliminated.
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