May 22, 2013
SAN JOSE, Calif — May 22, 2013 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the lineup for interviews at its “RTL Signoff Theater” at the 50th Design Automation Conference (DAC) to be held June 3-7, 2013 at the Austin Convention Center in Austin, Texas. Customers and partners will present their experiences with the development of register transfer level (RTL) signoff flows using Atrenta products.
[read more]
May 20, 2013
Sunnyvale, Calif. – May 20, 2013– Ausdia, the leading developer of timing constraints verification and management solutions that complement timing signoff for complex system-on-chip (SoC) designs, has been issued patent number US 8,438,517 B2 by the United States Patent and Trademark Office. The patent, which discloses automated techniques for identifying and managing the relationship between clock domains in an integrated circuit (IC) design, extends the company’s technology lead.
[read more]
May 16, 2013
LOUISVILLE, Colo. –– May 16, 2013 –– Industry luminaries from Freescale, National Instrument, Samsung, Qualcomm, Texas Instruments and UC Berkeley will all present keynotes at the 50th Design Automation Conference (DAC), the premier conference devoted to electronic design, design automation, embedded systems and software. The 50th DAC will be held at the Austin Convention Center in Austin, Texas from June 2-6, 2013.
[read more]
May 15, 2013
SAN JOSE, CALIF. –– May 15, 2013 –– ProPlus Design Solutions, Inc. (www.proplussolutions.com) announced today that Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 981) has deployed ProPlus’ NanoYield™ High-Sigma (HS) within its advanced technology development flow.
[read more]
May 14, 2013
SAN JOSE, CALIF. –– May 14, 2013 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software to enable design at a higher level of abstraction, today unwrapped its enhanced Cynthesizer™ SystemC-based high-level synthesis (HLS) product.
The new version includes low power synthesis capabilities, core synthesis algorithms, and a new SystemC integrated development environment (IDE).
[read more]
May 14, 2013
SAN JOSE, CALIF. –– May 15, 2012 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software to enable design at a higher level of abstraction, today announced that LG Electronics (www.lg.com) of Seoul, Korea, has adopted Cynthesizer™ SystemC high-level synthesis (HLS) for its next-generation digital television (DTV) design project.
[read more]
May 14, 2013
SAN JOSE, CALIF. –– May 14, 2013 –– Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company, will celebrate its 10th anniversary now through the 50th Design Automation Conference (DAC), where it will exhibit in Booth #2015 June 3-5 at the Austin Convention Center in Austin, Texas.
[read more]
May 13, 2013
LOUISVILLE, Colo. –– May 13, 2013 –– The Design Automation Conference (DAC), celebrating its 50th year as the premier conference devoted to electronic design, design automation, embedded systems and software, announces that Management Day will be on Tuesday June 4th 2013. The 50th DAC will be held at the Austin Convention Center in Austin, Texas from June 2-7, 2011. Management Day will begin at 10:30am on Tuesday, June 4, and is sponsored by Chip Estimate.
[read more]
May 9, 2013
Paul McLellan, SemiWiki
[read more]
May 8, 2013
Noida, UP — May 8, 2013 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced its recent relocation into an expanded R&D facility at A-12 & A-29, Sector-2, Noida, UP. The new facility houses Atrenta's current staff and meets near-term growth requirements, keeping pace with the company's global expansion plan.
[read more]
May 7, 2013
SAN JOSE, CALIF. –– May 7, 2013 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software to enable design at a higher level of abstraction, today launched the Forte Design Systems Channel (www.youtube.com/ForteDesignSystems) on YouTube as part of its enhanced education and training program.
[read more]
May 7, 2013
Paul Dempsey, Tech Design Forum
[read more]
May 6, 2013
Santa Clara, California - May 6, 2013 - Sage Design Automation (Sage-DA) has been founded to develop technology and products that automate the rule-based design and verification paradigm. Sage-DA was founded with initial investment from venture capital and angel investors including Alex Shubat, PhD, former President and CEO of Virage Logic (NASDAQ: VIRL, acquired by Synopsys in 2010) and Michael Burstein, PhD, EDA veteran and co-founder of multiple EDA companies. Coby Zelnik, former CEO of Sagantec, leads the company as President and CEO.
[read more]
May 5, 2013
Paul McLellan, SemiWiki
[read more]
May 2, 2013
Peggy Aycinena, EDACafe
[read more]
Apr 29, 2013
CAMPBELL, Calif., Apr 24, 2013 – IC Manage, Inc. today announced the availability of its fifth annual Global Design Management Report. This year’s report is on IP Reuse – Design and Verification and covers the results of a 372 respondent survey of SOC and IC design professionals; it spans design reuse, verification reuse, and dependency management.
[read more]
Apr 29, 2013
CAMPBELL, Calif. April 24, 2013 – IC Manage, Inc. today announced that Craig Shirley has joined the company as vice president of worldwide sales. Mr. Shirley will lead the company’s sales organization to extend its leadership in Design and IP Management.
[read more]
Apr 29, 2013
Paul Dempsey, Tech Design Forum
[read more]
Apr 26, 2013
LOUISVILLE, Colo. –– April 26, 2013 –– The Design Automation Conference (DAC), celebrating its 50th year as the premier conference devoted to electronic design, design automation, embedded systems and software, will feature seven tutorials and six workshops starting on Sunday, June 2, 2013. The 50th DAC will be held at the Austin Convention Center in Austin, Texas from June 2-6, 2013.
[read more]
Apr 25, 2013
Peggy Aycinena, EDACafe
[read more]
Apr 24, 2013
LOUISVILLE, Colo. –– April 24, 2013 –– Nanette Collins, a public relations consultant from Boston, was selected as the Marie R. Pistilli Women in Electronic Design Automation (EDA) Achievement Award recipient for 2013.
The award, named for DAC’s former organizer Marie Pistilli, is presented annually to an individual who has helped advance women in the EDA industry. It will be presented to Collins during the 50th Design Automation Conference (DAC) Monday, June 3, at 2:30 p.m. in the DAC Pavilion (Booth #509) in Austin, Texas. Immediately following, Ann Steffora Mutschler, senior editor at System-Level Design, will interview Collins. DAC will be held June 2-6 at the Austin Convention Center.
[read more]
Apr 22, 2013
LOUISVILLE, Colo. – April 22, 2013 – The Design Automation Conference (DAC), celebrating its 50th year as the premier conference devoted to electronic design, design automation, embedded systems and software, announces a panel session titled Affiliation Avenue – The Road to Success! sponsored by the Workshop for Women in Electronic Design (WWED). The panel session will take place on Monday June 3rd at 1:30pm as part of the 50th DAC, which will be held at the Austin Convention Center in Austin, Texas from June 2-6, 2013. The panel will be followed by the presentation of the 2013 Marie R. Pistilli Women in Design Automation Achievement Award and an interview with the recipient.
[read more]
Apr 18, 2013
Our second DAC 2013 preview article focuses on some of the panel sessions running both as part of the main conference and in the DAC Pavillion on the exhibition floor. We don’t have space to list all of them – these just caught our eye for a few of the reasons we outline below – and you probably want to check out the main DAC 2013 program because there is plenty of meat in there.
[read more]
Apr 17, 2013
What
Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, announces that it will participate to the Electronic Design Process Symposium (EDPS) 2013 in Monterey, CA on April 18, 2013.
[read more]
Apr 16, 2013
Paris, France – April 16, 2013 – Flexras Technologies, the provider of high performance partitioning software, today announced the release 3.2 of its WasgaTMCompiler Design Suite for FPGA-based prototyping. This new release supports the Xilinx® Virtex®-7 FPGA and includes new features that accelerate SoC rapid prototyping.
[read more]
Apr 16, 2013
SAN JOSE, Calif — Apr 16, 2013 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced that frobas GmbH will collaborate with Atrenta on the integration of their SpyGlass® CDC clock domain crossing verification product into frobas’ advanced SoC design flow. The terms of the collaboration will be managed as part of Atrenta’s SpyLinks™ partner program.
[read more]
Apr 16, 2013
Brian Bailey 4/16/2013 11:48 AM EDT Before we know it the Design Automation Conference will be upon us. While you and I may just have started planning for it, the program committee has almost finished and with this being a special year – DACs 50th anniversary, they have some new and exciting things for us. First is a new location. DAC has never been held in Austin before and only once in Texas. Why Austin? First, there are a lot of chip and IP companies in that area with a particular specialty being processors.
[read more]
Apr 15, 2013
LOUISVILLE, Colo. – April 15, 2013 – Offering the opportunity to enter the Design Automation Conference (DAC) and be part of the celebration, Atrenta, Jasper Design Automation, and Forte Design Systems are sponsoring three-day exhibit passes through the fifth annual “I LOVE DAC” campaign. DAC is celebrating its 50th year as the premier conference devoted to electronic design, design automation, embedded systems and software. This golden year for DAC will be filled with exciting exhibits, riveting keynotes, Designed in Texas sessions, networking events and much more. The conference and exhibition will be held at the Austin Convention Center in Austin, Texas from June 2-6, 2013.
[read more]
Apr 11, 2013
LOUISVILLE, Colo. –– April 10, 2013 –– The 50th Design Automation Conference (DAC), the premier conference devoted to electronic design, design automation, embedded systems and software, will feature 15 Pavilion Panel sessions in the program lineup for DAC 2013. Complementing the more in-depth DAC technical conference program, the DAC Pavilion hosts an eclectic mix of panels, presentations and interviews in Booth #509 on the exhibit floor. The 50th DAC will be held at the Austin Convention Center in Austin, Texas from June 2-6, 2013.
[read more]
Apr 10, 2013
SAN JOSE, California – April 2 2013 – Dr. Chenming Hu, TSMC Distinguished Professor of the Graduate School at the University of California, Berkeley, has been selected by the EDA Consortium (EDAC) and the IEEE Council of EDA (CEDA) as recipient of the 2013 Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation (EDA). .
[read more]
Apr 5, 2013
Paul Dempsey, Tech Design Forum
[read more]
Apr 5, 2013
Mike Demler, OpenSystems Media
[read more]
Apr 3, 2013
SAN JOSE, CALIF. –– April 2, 2013 –– ProPlus Design Solutions, Inc. (www.proplussolutions.com), the global leader for SPICE modeling solutions and the leading technology provider for Design-for-Yield (DFY) applications, today launched NanoSpice™, the next-generation high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation.
[read more]
Apr 2, 2013
SAN JOSE, Calif — Apr 2, 2013 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, will receive the “Bumper Crop” award from the Second Harvest Food Bank at their upcoming Make Hunger History celebration. The award is in recognition of Atrenta’s substantial year-over-year increase in contributions to Second Harvest Food Bank of 51 percent and the company’s continued support of the organization’s work over the years.
[read more]
Mar 14, 2013
Grenoble, France and San Jose, CA – March 14, 2013 – Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today announced new releases of Aceplorer 3.1 and AceThermalModeler 2.0.
[read more]
Mar 5, 2013
ACTON, MASS. –– March 5, 2013 –– Carbon Design Systems® Inc. (www.carbondesignsystems.com) announced today that its newest Carbon Performance Analysis Kit (CPAK™) featuring the ARM® Cortex™-R7 processor is available for download from the Carbon IP Exchange web portal (www.carbonipexchange.com).
[read more]
Feb 26, 2013
MUNICH, GERMANY and SANTA CLARA, CALIF. –– February 26, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) and formal equivalence checking solutions, and Oasys Design Systems (www.oasys-ds.com), provider of Oasys RealTime physical register transfer level (RTL) exploration and synthesis software, today announced they have signed an original equipment manufacturer (OEM) agreement.
[read more]
Feb 18, 2013
SAN JOSE, CALIF. –– February 18, 2013 –– Breker Verification Systems (www.brekersystems.com), The System-on-Chip (SoC) Verification Company, today unveiled an enhanced graphical user interface (GUI) for TrekSoC™, software that automatically generates self-verifying and synchronized C test cases to run on an SoC’s multiple heterogeneous embedded processors for faster and more thorough verification.
[read more]
Feb 12, 2013
SAN JOSE, CALIF. –– February 12, 2012 –– Forte Design Systems™ (www.ForteDS.com), the #1 provider of software products that enable design at a higher level of abstraction and improve design results, today announced its Cynthesizer™ high-level synthesis (HLS) is the first HLS software to support IEEE 1666™-2011 SystemC
[read more]
Feb 11, 2013
MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced the bundling of multiple verification tools into its new OneSpin 360™ DV Product Family.
[read more]
Feb 11, 2013
MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™ (www.onespin-solutions.com), provider of innovative formal assertion-based verification (ABV) solutions, announced immediate availability of 360™ EC-RTL, equivalence checking software that compares revisions of register transfer level (RTL) code.
[read more]
Feb 11, 2013
PARIS, France – February 11, 2013 - Reflex CES, a provider of custom embedded and complex systems, today introduced FPP25, a fast ASIC/SOC prototyping platform for emulating designs of up to 25-million ASIC gates using a stand-alone system. Based on Xilinx Virtex-7 2000T FPGAs, FPP25 exploits Reflex CES’ collaboration with Flexras, an EDA company specializing in FPGA design partitioning software, and Adacsys, a functional verification software provider, to offer design engineers an easy-to-use, next generation platform to speed up validation and verification of complex, high density digital designs.
[read more]
Feb 6, 2013
SAN JOSE, Calif., – February 4, 2013 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, today announced that Sanjiv Kaul has joined the company as President and Chief Executive Officer (CEO).
[read more]
Jan 23, 2013
Peggy Aycinena, EDACafe
[read more]
Dec 18, 2012
Santa Clara, California– December 18, 2012 -- Blue Pearl Software, the provider of EDA software that accelerates RTL signoff for FPGA designs, today announced it has added sales and support staff in North America due to the increased interest in using the Blue Pearl Software Suite for designs in the embedded, military and medical devices markets.
[read more]
Dec 18, 2012
PARIS-EVRY-France – December 12, 2012 - Reflex CES, a provider of custom embedded and complex systems, today announced the industry’s first release of the Reflex CES Aurora-like IP Core based on Altera FPGAs. The core enables interoperability between Xilinx Virtex-6 LXT and Altera Stratix IV and Stratix V GX FPGAs.
[read more]
Dec 13, 2012
Santa Clara, California and Tokyo, Japan – December 13, 2012 -- Blue Pearl Software, the provider of EDA software that accelerates RTL signoff for FPGA designs, today announced it has opened a Japan office in Tokyo, and appointed Katsuhiko Sakano as its Director of Sales.
[read more]
Dec 3, 2012
SAN JOSE, Calif — Dec 3, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today the 5.0 release of its SpyGlass® RTL analysis and optimization platform. This is also the first unified release of the SpyGlass and GenSys® platforms. The release contains extensive enhancements for performance, accuracy and usability, and many are the direct result of customer feedback.
[read more]
Nov 26, 2012
EVEN YEHUDA, Israel — Nov 26, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today a significant expansion in its sales and support operations in Israel with the addition of a dedicated sales manager and a customer solutions architect.
[read more]
Nov 12, 2012
SAN JOSE, Calif — Nov 12, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, is the number two supplier of RTL power analysis tools according to the 2012 Market Trends Report published by Gary Smith EDA. The popular report on the EDA market shows Synopsys as the number one vendor in the segment with Atrenta leading the nearest competitor by seven percent.
[read more]
Nov 9, 2012
MONROVIA, California – November 7, 2012 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), closed fiscal 2012 (year ending May 2012) with strong growth across a number of key business and technology metrics. The company celebrated its 25th year in business with growth in revenues, new customers, product offerings, technology partnerships and foundry relationships.
[read more]
Nov 6, 2012
Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that Episil Technology, Inc., a pure-play foundry house specializing in epitaxial and silicon wafer foundry services for power and analog semiconductor products, has selected the company’s AFS Nano SPICE simulator for analog and power device characterization.
[read more]
Nov 1, 2012
SAN JOSE, Calif and HSINCHU, Taiwan, R.O.C. — Oct 31, 2012 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, with TSMC announced today the planned availability of IP Kit 2.0. Based on the SpyGlass® RTL design platform, IP Kit is a fundamental element of TSMC’s soft IP9000 Quality Assessment program that assesses the robustness and completeness of soft, or synthesizable IP. IP Kit 2.0 has undergone extensive beta testing by TSMC soft IP alliance partners: Digital Media Professionals Inc., Dolphin Integration, Sonics, Inc. and Vivante Corporation. IP Kit 2.0 will be fully supported on TSMC-Online and available to all TSMC’s soft IP alliance partners on Nov. 20, 2012.
[read more]
Oct 24, 2012
Santa Clara, California – October 24, 2012 -- ARM® TechCon™-- Blue Pearl Software, the provider of EDA software that accelerates RTL signoff for FPGA designs, today announced it is a new member in the ARM Connected Community, the industry’s largest ecosystem of ARM technology-based products and services. As part of the ARM Connected Community, Blue Pearl gains access to a full range of resources to help it market and deploy its innovative Blue Pearl Software Suite for FPGA design to enable developers to get their ARM Powered® products to market faster.
[read more]
Oct 23, 2012
SAN JOSE, Calif. -October 19, 2012 -Blue Pearl Software, Inc., the provider of EDA software that accelerates RTL signoff for FPGA designs, today, announced that it is shipping Release 6.1 of its Blue Pearl Software Suite, for Windows and Linux operating systems. The new version includes enhancements that improve and further automate the FPGA design process, including one of its biggest design bottlenecks - critical path analysis.
[read more]
Oct 11, 2012
SANTA CLARA, CA – October 10, 2012 - ATopTech, the leader in next generation physical design solutions, today announced that Aprisa™ and ApogeeTM, the company’s place and route solution, are included in TSMC’S 20nm Reference Flow. TSMC’S 20nm process technology delivers better performance and lower power consumption than previous generations. TSMC and ATopTech collaborated in incorporating ATopTech tools in the 20nm Reference Flow to address the increasing design challenges for 20nm.
[read more]
Oct 10, 2012
San Jose, CA – Oct 10, 2012
What:
Atrenta Speaker Anuj Kumar will present in the IP Track Session, titled - TSMC IP Kit V2.0 - Enhancing Soft IP Quality Standards
[read more]
Oct 8, 2012
SANTA CLARA, Calif., – October 5, 2012 – Calypto® Design Systems, Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power reduction, today announced that Core Logic Inc., Korea’s leading fabless semiconductor manufacturer, has adopted PowerPro® CG as their primary power optimization tool for designing their complex system-on-chip (SoC) products.
[read more]
Oct 3, 2012
SAN JOSE, Calif — Oct 3, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today that its products took three of the top five positions in the popular DeepChip DAC User Survey. The survey, conducted by John Cooley and published on the DeepChip portal, summarizes user inputs regarding the top products at DAC. This year’s survey included detailed responses from 178 EDA tool users.
[read more]
Aug 9, 2012
LOS GATOS, Calif., August 9, 2012-- IC Manage, Inc. today announced that Altera Corporation (NASDAQ: ALTR), the world’s leading provider of programmable logic devices, has signed a multi-year license agreement for the IC Manage Global Design Platform™ (GDP), including IP Central™, for use across the company’s worldwide development sites. Altera adopted IC Manage design management solutions to achieve higher IP reuse, trace bug interdependencies, and improve multi-site collaboration.
[read more]
Jul 31, 2012
SANTA CLARA, Calif., – July 31, 2012 – Calypto® Design Systems, Inc., a leader in SOC design and optimization, today announced record results for the 49th Design Automation Conference (DAC). Calypto attributes its DAC success to the recent launch of Catapult® Low-Power High-Level Synthesis (HLS), the first HLS tool to include power as a top level design constraint, and the #1 ranking of their PowerPro product family for RTL power reduction on John Cooley’s ‘Must See List for DAC 2012’ on DeepChip.com.
[read more]
Jul 25, 2012
YOKOHAMA, Japan and SUNNYVALE, Calif. – July 25, 2012 - Real Intent, Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today that its Japan office, Real Intent KK, has expanded. The new offices are located at the Industry & Trade Center Building in Yokohama. The newly appointed staff includes Yasuo Torisawa, Country Manager at Real Intent KK and Kazutaka Kanda, Senior Application Engineering Manager.
[read more]
Jun 25, 2012
SAN JOSE, Calif — June 20, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, today announced that it has acquired NextOp Software, Inc., a leading provider of assertion synthesis technology. Atrenta’s products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp’s products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company’s products creates a more complete SoC Realization platform.
[read more]
Jun 21, 2012
[read more]
Jun 19, 2012
Cindy Wilson, EVE
[read more]
Jun 18, 2012
Dave Bursky, Chip Design Magazine
[read more]
Jun 10, 2012
Richard Goering, Cadence Design Systems, Inc.
[read more]
Jun 8, 2012
Amelia Dalton, EE Journal
[read more]
Jun 7, 2012
Bernard Cole, UBM Tech
[read more]
Jun 7, 2012
Mark LaPedus, Chip Design
[read more]
Jun 7, 2012
Frank Schirrmeister, Cadence Design Systems, Inc.
[read more]
Jun 6, 2012
Mark LaPedus, Chip Design
[read more]
Jun 5, 2012
JL Gray, Verilab.
[read more]
Jun 5, 2012
Santa Clara, California – June 4, 2012 – Sagantec today announced that Vanguard International Semiconductor Corporation (VIS) has adopted Sagantec's process migration solution for its standard cell libraries to be able to quickly migrate its IP or modify it to accommodate customer needs.
[read more]
Jun 5, 2012
SAN FRANCISCO, Calif — June 4, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today at the 49th Design Automation Conference (DAC) the availability of a Fast Lint methodology for its SpyGlass RTL analysis and optimization platform. The new capability is part of Atrenta’s GuideWare reference methodology, and tests on a wide range of designs have shown a 4X to 9X speed improvement while still delivering accurate, low noise results.
[read more]
Jun 4, 2012
June 4, 2012, San Francisco, CA – AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification, today released new design-oriented features in its Design and Verification Tools (DVT) IDE. These features enable design engineers to easily understand how a signal propagates in a design, connect two modules across the design hierarchy, and inspect and document a module structure.
[read more]
Jun 1, 2012
SAN JOSE, California–June 1, 2012 -Blue Pearl Software, Inc., a leading provider of EDA software which accelerates electronic design implementation, announced today that Northwest Logic, Inc., a leading provider of high-performance, easy-to-use, Intellectual Property (IP) cores, uses Blue Pearl’s Analyze to maximize the quality of its IP cores.
[read more]
May 31, 2012
Montpellier, France, 31st May 2012. Cortus, a technology leader in cost effective, silicon efficient 32-bit processor IP, launches the latest member of their processor family: the high performance, high throughput APS5. The APS5 combines good integer computational performance with a high maximum clock frequency. This processor IP is designed for ASICs requiring more complex processor subsystems such as those with instruction and data caches or co-processors. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.
[read more]
May 31, 2012
SAN JOSE, Calif — May 30, 2012 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, announced today the addition of an interview program at the 49th Design Automation Conference (DAC) to be held June 3-7, 2012 at San Francisco’s Moscone Center. Customers, partners and investors will comment on how Atrenta’s SpyGlass® RTL analysis platform helps their business.
[read more]
May 30, 2012
MONROVIA, California – May 30, 2012–Tanner EDA, the catalyst for innovation for the design, layout, and verification of analog and mixed-signal integrated circuits (ICs), and Australian Semiconductor Technology Corporation (ASTC), providing global consulting services for semiconductors, software and systems, are collaborating to deliver analog /mixed signal ASIC design services and solutions globally.
[read more]
May 30, 2012
Dylan McGrath, EE Times
[read more]
May 29, 2012
SANTA CLARA, California–May 29, 2012 -Blue Pearl Software, Inc., a leading provider of EDA software that accelerates field-programmable gate array (FPGA) implementation, announced that it has joined the Xilinx Alliance Program. Xilinx Inc. is the worldwide leader and developer of All Programmable devices. As a result of its Xilinx collaboration, Blue Pearl announces improved productivity for Xilinx Vivado™ Design Suite users, by reducing development time, run time and the number of design iterations.
[read more]
May 29, 2012
SANTA CLARA, Calif., – May 29, 2012 – Calypto® Design Systems, Inc., a leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) low power optimization, today announced Catapult® Low-Power (LP), the industry's first production quality, high-level synthesis (HLS) tool that adds power as an optimization goal. By leveraging Calypto’s existing best in class power analysis and optimization technology, Catapult LP provides a closed loop optimization across power, performance and area (PPA) to address the challenges of power-aware design.
[read more]
May 29, 2012
SUNNYVALE, Calif. – May 29, 2012 - Real Intent, Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-off of electronic designs, announced today the release of version 4.1 of its Meridian™ Clock Domain Crossing (CDC) analyzer and the release of version 1.5.1 of its Ascent™ Lint tool. These new releases provide significant advances over the 2011 versions of the software.
[read more]
May 29, 2012
SAN FRANCISCO, CA– Design Automation Conference (DAC) – May 29, 2012 – Flexras Technologies, an EDA company specializing in partitioning for FPGA-based prototyping, today announced Wasga Compiler, a software tool that boosts multi-FPGA design performance. Wasga Compiler is unique and is the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. It typically delivers a 10X clock frequency increase, runs blazingly fast, handles multi-billion ASIC gates equivalents designs, and maps them to any Altera or Xilinx board, whether it’s off-the-shelf or custom.
[read more]
May 25, 2012
Campbell, CA – May 24, 2012 – Silicon Frontline Technology, Inc. (SFT) an Electronic Design Automation (EDA) company, in the 3D parasitic extraction and analysis software market, announced new versions of its flagship products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures, and a new product P2P (Pont-to-Point) for IR drop analysis.
[read more]
May 24, 2012
Montpellier, France, 22nd May 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP, announces the release of the latest member of their processor family: the energy efficient APS3R. The APS3R builds on experience with the earlier APS3 core but delivers improved computational performance. For more demanding embedded applications a dual core configuration is possible.
[read more]
May 24, 2012
Montpellier, France and Marina del Rey, California, 24th May 2012. Cortus, a technology leader in ultra low power, silicon efficient 32-bit processor IP and MOSIS, a provider of low-cost prototyping and small volume production services for custom ICs, announced the signing of a sales representative agreement. Under the agreement, MOSIS will offer the Cortus APS3R and associated peripherals to their customers. The deal will support the licensing of Cortus IP from design through prototyping to volume production with MOSIS.
[read more]
May 18, 2012
Brian Bailey, EE Times
[read more]
May 15, 2012
Brian Bailey, EE Times
[read more]
May 14, 2012
Peggy Aycinena, EDACafe
[read more]
May 6, 2012
Peggy Aycinena, EDACafe
[read more]
Mar 14, 2012
AUSTIN, Texas — Apple Inc. is investing $304 million in a new campus and more than doubling its workforce in the Texas capital, boosted by a $21 million incentive from a state fund designed to attract high-tech companies, Gov. Rick Perry said Friday.
[read more]