Squeeze Play

For the past decade, Electronic System Level (ESL) has been widely seen as the future of EDA.   And no wonder!  Think of the productivity gains if chip designers could define what they want a chip to do... not how the circuitry is supposed to do it.  Alas, the promise of ESL was continually scuttled by the demands of ever-more-complex manufacturing process.  Try as it might, ESL was never able to automate the Register Transfer Level (RTL) "tweaking" required to turn a design into working silicon. 

All of that looks poises to change, though.  Innovations at the foundries, downstream from RTL, are combining with a new set of ESL tools to turn RTL tweaking (and the tools designers use to tweak) into an industry backwater.  As a result, we may be on the cusp of a major restructuring of the entire EDA industry.  “We are finally reaching a point similar to when RTL took over from gate-level design,” says EDA analyst Gary Smith.   It’s a forecast he’s made before... and now it’s finally happening.

A SHIFT OF POWER
Software markets, including EDA, tend to go through a cycle that consists of three general stages: 1) innovation, 2) standardization, and 3) consolidation.  During the innovation phase, small companies (and skunk-works inside larger firms) create new technology which appeals to early innovators.  Once the technology establishes itself as feasible, there’s always a drive to standardize on a specific way of doing things.  As a result, existing products become undifferentiated, leading to market consolidation.

The EDA industry behaves the same way, but faster than other software markets, due to the need to address the constantly changing targets of new process nodes.  Even so, a larger cycle has played itself out in the EDA industry as a whole, with the last major transition being the abandonment of gate-level design for RTL programming.  That happened a couple of decades ago, and the EDA industry is overdue for a major change.

Interestingly, the EDA industry, taken at the macro level, exhibits all the characteristics of a software market at the tail end of an innovation cycle.  As shown in Graphic 1, in 2008, the percentage of quarterly revenue captured by small vendors has grown by around a third since 2001, to the point where the big three, together, control just a little more than half of the industry.  That’s phenomenal, considering that the big three all have business models that depend heavily upon acquisition.  If the big three had organic growth strategies, their revenues would probably account for even far larger market share.

Even more importantly, smaller companies are dominating the growth of the market, according to Smith.  “We are seeing rapid growth rates of 30 to 50 percent in these firms most of which are working on ESL and other EDA tools that permit designers to work at a higher level of abstraction,” he says.  In other words, the long-heralded ESL revolution is apparently at our doorsteps.  The big questions are:  Why ESL now?  And what does it mean for the industry as a whole?

WHY ESL NOW?
To understand why ESL is suddenly a big deal for EDA, it’s important first to understand why the ESL revolution kept misfiring. 

The culprit was Moore’s Law.  When process nodes moved sub-micron, each progressive node kept forcing more and more process-specific rules higher up the design chain.  The industry coped with this complexity by launching initiatives for Design For Manufacturing (DFM).  DFM, however, runs contrary to ESL trend, because it forces designers to take notice of, and make allowances for, the details of specific manufacturing processes.

As a result, the EDA tools that translated and tested the ESL designs weren’t capable of creating efficient circuitry.  A prime example was timing closure, which typically forced designers to optimize each block of a chip at the RTL level in order to ensure that each block could achieve closure.  While automated tools could create multiple “automated” RTL implementations, it was often only through tweaking the RTL that you’d end up with a usable chip.

What emerged was a design chain that had three engineering levels.  At the top were a plethora of ESL tools, where designers could look at chip design at a higher level of abstraction.  At the bottom level were a set of process-specific EDA tools that helped translate RTL into what was needed in a specific process at a specific foundry.  And in the middle, were the traditional RTL-level tools, which designers still used to translate and tweak ESL designs into something closer to what a foundry process might understand.

Much of that is changing, however, as the result of six industry trends:

1. Improvements in process specific EDA.  The foundries have been working hard to make process-specific tools more powerful, thereby making it easier for high-level designers to ignore process-specific complexities.  “What we’re seeing is the emergence of something that’s very much like the ASIC model of the past, but with the foundries acting as the ‘one stop shop’ for ESL designers,” explains the EDA analyst Gary Smith of GarySmithEDA.com.
   
2. Improvements in ESL-generated RTL.  ESL tool makers have greatly improved the quality of the RTL that their tools produce, according to Brett Cline, vice president of marketing at Forte Design Systems, a maker of such tools.  “We can now create RTL code that don’t have timing problems because we’re building the circuitry from a library of known parts that work well with the downstream tools,” he explains.
   
3. Increased dependence upon IP.  IP now accounts for 80 to 90 percent of most chip designs, according to Allen Watson, the product manager at MIPS who handles their ESL activities.  Because IP can be pre-qualified for various manufacturing processes, ESL definitions of those IP block can more accurately represent the actual behavior of the chip. “While we develop our IP at the RTL level, we now provide SOC designers with an ESL model that they can use for their virtual prototyping,” explains Watson.
   
4. Decreased need for efficient circuitry.  Because each successive node provides geometrically more circuitry on a chip, it’s becoming less important for chip designers to create tight, efficient circuitry. While ESL tools cannot create chip designs that are as efficient as if a trained engineer had optimized each block by hand, with each successive node the cost of additional gates and silicon becomes radically reduced, making ESL a more viable alternative to RTL coding.
   
5. Increased complexity of design.  ESL solves some of the problems of complexity inherent in the design chips for the latest process nodes.  “Today’s SOCs contain so many different elements, which much interact in so many different ways, it simply overwhelms the ability of a human engineer working at the RTL level to understand everything that’s going on,” says Lauro Rizzatti, general manager of EVE-USA, a maker of hardware emulators.
   
6. Increased importance of software.  ESL allows chip designers to work more closely with software designers on the functionality of the entire system, according to Simon Davidmann, CEO of Imperas, a company that makes multicore embedded tools.  “Embedded software designers are beginning to behave and think like chip designers and vice versa,” he says.  “It seems clear that there’s going to be a certain amount of merging of those disciplines.”
   

In other words, the economics of chip design is combining with technological improvements in a way that threatens to marginalize RTL as a chip design technology.  And if that happens, it means that the EDA industry is on the brink of a major transformation.

WHITHER THE INDUSTRY?
How will the EDA industry look in the future?  If RTL tools indeed become an industry backwater, EDA is likely to bifurcate into two very distinct segments: process-specific EDA and software-centric EDA.

Process specific EDA will be a small market in terms of the numbers of seats, simply because the expense of building fabs at the newest nodes is reducing the number of companies who can afford to participate.  Even so, such tools will provide a lot of value, so there will definitely be money for EDA vendors in helping foundries and ASIC manufacturers hone their ability to turn ESL-generated RTL into actual silicon as quickly as possible.

Two of the big three, Synopsys and Mentor, have been particularly active working with the foundries on such tools, according to Risto Puhakka, vice president at VLSI Research, a firm that studies the semiconductor industry.  “Both of these firms have developed a robust manufacturing side of the business, resulting in relatively strong portfolios compared to Cadence,” he says.

Software-centric EDA will combine what we now know as ESL with a variety of software tools that work with ESL tools to help teams of chip designers and software designers to work together to create SOCs.

That could be a big-money business for EDA firms, according to Smith, especially if ESL design absorbs the activities traditionally considered part of embedded programming.  “Today, the average cost for tools for an embedded designer is around $10k, but with additional functionality, like parallel processing, multicore, debugging, hyperthreading, and so forth, each seat could be worth $40k or more.”  That would translate into some $16 billion in additional revenue that EDA firms could potentially capture.

Not surprisingly, Synopsys has already begun making acquisitions to strengthen its portfolio of ESL tools, according to Frank Schirrmeister, the company’s director of product marketing for system-level solutions.  He specifically cites the acquisition of Synplicity in May of 2008 and ChipIT in the following December as strengthening Synopsys’s capabilities in the virtual prototyping arena.

Cadence, too, has been working hard to position itself in this area, particularly when it comes to the creation and verification of ESL-designed IP.  “ESL helps customers manage their risks when developing new chips because it makes it easier for companies to create, verify and use IP,” explains Steve Glaser, Cadence’s corporate VP of strategic marketing.  “You now use ESL to build a custom RTL that’s optimized for your target application.”

Even so, it’s unclear whether the big three vendors will dominate the ESL segment,. according to Smith, who notes that Cadence’s shift in direction is late.  “For the first time in years, EDA industry growth was negative last year, largely due to the collapse of Cadence,” he says, a phenomenon that he attributes to the fact that Cadence’s tools tended to address the needs of the mainstream rather than the power users who have been gravitating to ESL.

This is not to say that traditional EDA tools vanish completely.  Circuits that include analog components, for example, may always require significant hands-on engineering. However, as ESL becomes an increasingly important segment, and RTL goes the way of gate-level design, there’s little doubt that things will be different.  “There’s going to be some big changes as in the industry as companies scramble to cope,” says Smith. That’s not bad news for the industry as a whole, but it could mean that the era of the big three’s dominance may be finally drawing to a close.

GRAPHIC 1: PROPORTION OF EDA REVENUE TO “BIG THREE” VENDORS

RAW DATA:

Source: EDAC, Annual Reports

SOURCES:

• Allen Watson, MIPS. Contact: Sarmishta Ramesh, 303-327-5459 sramesh@hoffman.com
• Brett Cline, Forte Design Systems.  Contact: Nanette Collins, 617-437-1822, nanette@nvc.com
• Frank Schirrmeister, Synopsys.  Contact: Sheryl Gulizia, (866) 675-1568, sgulizia@synopsys.com
• Gary Smith, GarySmithEDA, 408)985-2929, gary@garysmithEDA.com
• Lauro Rizzatti, EVE-USA. Contact: Nanette Collins, 617-437-1822, nanette@nvc.com
• Risto Puhakka, VLSI Research, 408-453-8844, rjp@vlsiresearch.com
• Simon Davidmann, CEO of Imperas.  Contact: Nanette Collins, 617-437-1822, nanette@nvc.com
• Steve Glaser, Cadence.  Contact: Dean Solov, 408-944-7226, dsolov@cadence.com