Workshop 4: DAC Workshop: Low-Power Design with the New IEEE 1801-2013 Standard
Sunday, June 2, 2013
Time: 1:00 PM — 5:00 PM
Low-Power Design and Power Analysis
|Organizer: ||Pete Hardee - Cadence Design Systems, Inc., San Jose, CA|
|Speakers: ||Qi Wang - Cadence Design Systems, Inc., San Jose, CA|
| ||Erich Marschner - Mentor Graphics Corp., Ellicott City, MD|
| ||Sushma Honnavara-Prasad - Broadcom Corp., Santa Clara, CA|
| ||John Biggs - ARM, Inc., Cambridge, United Kingdom|
| ||Jeffrey Lee - Synopsys, Inc., Mountain View, CA|
The latest version of the IEEE Std P1801 (Standard for Design and Verification of Low Power Integrated Circuits) was ratified by IEEE-SA on 6th March 2013. The new standard will be known as IEEE 1801-2013. The proposed presenters are all members of the IEEE 1801 working group, and are technical experts on the subject.
The workshop will cover an introduction to the low power design intent concepts and methodologies fundamental to IEEE 1801, as well as detailed discussion of the main changes from the previous version (IEEE 1801-2009). The workshop will concentrate on the standard, its underlying semantics and intended methodologies, in the eyes of the expert 1801 working group members, illustrated by real world examples. Showcasing capabilities of EDA vendor tools is not the focus of this workshop.
This will be a half-day (4-hour) workshop.
for additional event details.