Workshop 6: IP Workshop: Driving Quality to the Desktop of the DAC Engineer
Sunday, June 2, 2013
Time: 1:00 PM — 5:00 PM
|Organizer: ||McKenzie Mortensen - IPextreme, Campbell, CA|
|Speakers: ||Warren Savage - IPextreme, Campbell, CA|
| ||Dan Kochpatcharin - Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan|
| ||Mike Gianfagna - Atrenta Inc., San Jose, CA|
| ||Frank Ferro - Sonics, Inc., Milpitas, CA|
| ||Michael Cizi - IPextreme, Unterföhring, Germany|
| ||Richard Zbranak - Atrenta Inc., Austin, TX|
| ||Sveta Avagyan - Sonics, Inc., Milpitas, CA|
| ||John Bainbridge - Sonics, Inc., Milpitas, CA|
This workshop will demonstrate a complete flow, using de facto industry standards, for designing, packaging, and integrating semiconductor IP, insuring that quality metrics are observed and preserved throughout the flow to the DAC engineer’s desktop. A variety of leading companies will be part of the workshop, each presenting how their individual products work together in a cohesive fashion for the benefit of the SoC designer.
The companies and their contributions to the workshop are as follows:
TSMC will discuss the TSMC 9000™ quality standards and explain how they are beneficial for both IP providers and IP consumers.
Atrenta will demonstrate the use of SpyGlass® and its IP Kit™ for the analysis of IP against a set of standard quality metrics.
Sonics will demonstrate the creation of configurable IP and the manner in which it is validated and checked against quality metrics using the TSMC Soft IP Kit 2.0 flow.
IPextreme will demonstrate the use of Xena™ for storing and managing completed IP products and will also showcase how users can configure IP on-the-fly and re-verify the quality metrics produced from SpyGlass® in the Cloud.
The IP Workshop will realistically showcase how engineers from different companies use their proprietary tools and technology to work together. The result of this collaboration is the creation of high quality, first-time-correct products. Because the flow delves into a number of areas in the design and use of semiconductor IP, the workshop’s appeal and relevance is wide. There will be ample time provided for open discussion throughout the workshop—audience members are encouraged to ask questions and share their thoughts and impressions at each stage of the flow. The workshop will conclude with a roundtable session with the presenters.
for additional event details.