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DAC 2013 AUSTIN, TX | JUNE 2-6
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Friday, May 31

TimeTypeTitleLocation
9:00 AM Colocated Conferences Electronic System Level Synthesis Conference (ESLsyn) 15


Sunday, June 02

TimeTypeTitleLocation
8:00 AM Colocated Conferences IEEE International Symposium on Hardware Oriented Security and Trust 17AB
8:00 AM Colocated Conferences ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) 18AB
8:00 AM Colocated Conferences Design Automation Summer School 4ABC
8:30 AM Workshops Workshop 1: They Are All Networks! Analysis and Optimization for Electronics, Water, Electricity, Bio. A DAC Associated Workshop 13AB
9:00 AM Colocated Conferences NSF/CRA/CCC Workshop on Extreme-Scale Design Automation at DAC 8ABC
9:00 AM Colocated Conferences Microelectronic Systems Education (MSE) Austin Hilton
9:00 AM Workshops Workshop 3: 2013 DAC Workshop on Embedded Systems for Energy-Efficient Smart Infrastructures (ESSI) 18D
9:00 AM Workshops Workshop 2: DAC Workshop on Modeling of Biological Systems (MoBS) 14
1:00 PM Workshops Workshop 4: DAC Workshop: Low-Power Design with the New IEEE 1801-2013 Standard 18C
1:00 PM Workshops Workshop 6: IP Workshop: Driving Quality to the Desktop of the DAC Engineer 11AB
2:00 PM Workshops Workshop 5: DAC Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-oriented Environments 12AB
5:00 PM Additional Meetings Gary Smith EDA Pre-DAC Address Ballroom ABC
5:30 PM Networking Welcome Reception Outside Ballrooms ABC
7:00 PM Additional Meetings EDAC / CEDA Phil Kaufman Award Presentation Ballroom ABC


Monday, June 03

TimeTypeTitleLocation
7:15 AM Additional Meetings Synopsys Partner Breakfast: Optimizing Implementation of Performance- and Power-Balanced Processor Cores Hilton Grand Ballroom H
8:00 AM Additional Meetings Customer Insights: Success with Synopsys Galaxy Implementation Platform 10AB
9:00 AM Colocated Conferences IEEE International Workshop on Design for Manufacturing and Yield (DFM&Y) 18AB
9:15 AM Pavilion Panels Gary Smith on EDA: Trends and What's Hot at DAC Booth 509
10:00 AM Additional Meetings 26th ACM SIGDA University Booth at the 50th Design Automation Conference 4th Floor
10:15 AM Visionary Talk VISIONARY TALK: Walden C. Rhines - Chairman and Chief Executive Officer, Mentor Graphics Corp. Ballroom ABC
10:25 AM Keynotes Embedded Processing – Driving the Internet of Things Ballroom ABC
11:00 AM Designed in Texas Austin Processor History and Three DSPs Hall 5
11:00 AM Monday Tutorials Tutorial 1: Modeling, Abstraction, and Verification of Non-Volatile Memories 11AB
11:00 AM Monday Tutorials Tutorial 2: Methodology for Continuous 24x7 Verification and Coverage 12AB
11:00 AM Monday Tutorials Tutorial 3: Winning in Monte Carlo: Managing Simulations Under Variability and Reliability 13AB
11:00 AM Monday Tutorials Tutorial 4: A Practical Guide to Packaging IP and Assembling SoCs Using the IP-XACT- IEEE1685 Standard 14
11:00 AM Monday Tutorials Tutorial 5: Supercharge Your GPU: Developing and Optimizing OpenGL Applications Using a Native IDE Across Virtual and Physical Targets 15
11:00 AM Monday Tutorials Tutorial 6: Why Programming Many-Core is Not Mission Impossible 16AB
11:00 AM Monday Tutorials Tutorial 7: Avoiding Core Meltdown! - Adaptive Techniques for Power and Thermal Management of Multi-Core Processors 18C
11:15 AM Pavilion Panels Interview with Dr. Chenming Hu, Phil Kaufman Award Recipient Booth 509
11:30 AM Additional Meetings Synopsys Lunch: Advance Your Mixed-Signal Verification Techniques to the Next Level Hilton Grand Ballroom G
11:30 AM Additional Meetings SYNOPSYS LUNCH: THE MANY FACES OF ADVANCED TECHNOLOGY Hilton Grand Ballroom H
11:30 AM Additional Meetings Has “Timing Signoff Innovation” Become an Oxymoron? What Happened and How Do We Fix It? Austin Convention Center, Fourth Floor, Ballrooms
12:00 PM Additional Meetings Si2 25th Anniversary Lunch 9ABC
1:30 PM Designer Track Panel: Cloud Server War – Embedded Processor Battle Ground: Austin Hall 5
1:30 PM Additional Meetings Winning the Hardware Design Race Ballroom G
1:30 PM Pavilion Panels WWED Event: Affiliation Avenue: The Road to Success Booth 509
2:00 PM Monday Tutorials Tutorial 1: Modeling, Abstraction, and Verification of Non-Volatile Memories 11AB
2:00 PM Monday Tutorials Tutorial 2: Methodology for Continuous 24x7 Verification and Coverage 12AB
2:00 PM Monday Tutorials Tutorial 3: Winning in Monte Carlo: Managing Simulations Under Variability and Reliability 13AB
2:00 PM Monday Tutorials Tutorial 4: A Practical Guide to Packaging IP and Assembling SoCs Using the IP-XACT- IEEE1685 Standard 14
2:00 PM Monday Tutorials Tutorial 5: Supercharge Your GPU: Developing and Optimizing OpenGL Applications Using a Native IDE Across Virtual and Physical Targets 15
2:00 PM Monday Tutorials Tutorial 6: Why Programming Many-Core is Not Mission Impossible 16AB
2:00 PM Monday Tutorials Tutorial 7: Avoiding Core Meltdown! - Adaptive Techniques for Power and Thermal Management of Multi-Core Processors 18C
2:00 PM Additional Meetings Low Power Standardization Futures Meeting (co-sponsored by Si2 and the IEEE DASC) 9ABC
2:30 PM Pavilion Panels Interview with the Nanette Collins, 2013 Marie R. Pistilli Women in EDA Award Recipient Booth 509
3:00 PM Additional Meetings Cooley's DAC Troublemaker Panel Ballroom G
3:15 PM Pavilion Panels Will Data Explosion Blow Up the IC Design Flow? Booth 509
4:00 PM Visionary Talk VISIONARY TALK: Lip Bu Tan - President and Chief Executive Officer, Cadence Design Systems, Inc. Ballroom ABC
4:10 PM Keynotes Looking Ahead to 100 Years – Platform Engineering Ballroom ABC
4:30 PM Additional Meetings Annual Si2 Open Reception 9ABC
5:00 PM Global Forum Global Forum - Ribbon Cutting Ceremony Booth 137
5:00 PM Monday Tutorials Tutorial 1: Modeling, Abstraction, and Verification of Non-Volatile Memories 11AB
5:00 PM Monday Tutorials Tutorial 2: Methodology for Continuous 24x7 Verification and Coverage 12AB
5:00 PM Monday Tutorials Tutorial 3: Winning in Monte Carlo: Managing Simulations Under Variability and Reliability 13AB
5:00 PM Monday Tutorials Tutorial 4: A Practical Guide to Packaging IP and Assembling SoCs Using the IP-XACT- IEEE1685 Standard 14
5:00 PM Monday Tutorials Tutorial 5: Supercharge Your GPU: Developing and Optimizing OpenGL Applications Using a Native IDE Across Virtual and Physical Targets 15
5:00 PM Monday Tutorials Tutorial 6: Why Programming Many-Core is Not Mission Impossible 16AB
5:00 PM Monday Tutorials Tutorial 7: Avoiding Core Meltdown! - Adaptive Techniques for Power and Thermal Management of Multi-Core Processors 18C
6:00 PM Additional Meetings Synopsys PrimeTime SIG Event:Technology Panel – Advanced ECO Methodology Brazos Hall
8:00 PM Networking Kickin' It Up In Austin - DAC Party (Off Site) Austin City Limits Live at the Moody Th


Tuesday, June 04

TimeTypeTitleLocation
12:00 AM Additional Meetings A. Richard Newton Young Student Fellow Program Various
7:15 AM Additional Meetings Synopsys Partner Breakfast: Ready for Deploying GLOBALFOUNDRIES’ 14xm FINFETS in Mobile SoC Design Hilton Grand Ballroom G
8:00 AM Additional Meetings The Cadence System-to-Silicon Verification Breakfast Austin Convention Center, Fourth Floor, Ballrooms
8:30 AM Keynotes General Session/Award Presentations Ballroom ABC
9:15 AM Visionary Talk VISIONARY TALK: Aart J. de Geus - Chairman and co-Chief Executive Officer, Synopsys, Inc. Ballroom ABC
9:25 AM Keynotes New Challenges for Smarter Mobile Devices Ballroom ABC
10:15 AM Pavilion Panels Hogan’s Heroes: The EDA Hunger Games! Booth 509
10:30 AM Technical Panels Advanced Node Reliability: Are We in Trouble? 16AB
10:30 AM Special Sessions My IP is Better than Yours, but Does Anyone Care? 12AB
10:30 AM Designed in Texas Physical Design I Hall 5
10:30 AM Designer Track System Design Approaches 18C
10:30 AM Paper Sessions Emerging Mapping and Management Algorithms for Parallel Embedded Systems 11AB
10:30 AM Paper Sessions Lay it out, Analog! 13AB
10:30 AM Special Sessions Designing and Modeling Biology Continues: Hurdles and Progress 14
10:30 AM Paper Sessions Transformations in FPGA Design and Productivity 15
10:30 AM Management Day DAC Management Day 2013 17AB
11:30 AM Additional Meetings CUSTOM DESIGN LUNCH: ADDRESSING CUSTOM DESIGN CHALLENGES WITH LAKER Austin Hilton Grand Ballroom G
11:30 AM Pavilion Panels Great Expectations: Analog Mixed Signal Spectacle at the Design Border Booth 509
11:45 AM Additional Meetings Synopsys Lunch: SoC Leaders Verify with Synopsys Hilton Grand Ballroom H
12:00 PM Designer Track Poster Session 1 Hall 5
12:00 PM Global Forum Global Forum Booth 137
12:00 PM Additional Meetings IEEE CEDA Presents: Cyber-Physical Systems: A Rehash or A New Intellectual Challenge? 18AB
12:00 PM Additional Meetings SIGDA EC Meeting 5A
12:00 PM Additional Meetings IPL Alliance Dinner: IPDKS: A Thriving PDK Standard Hilton Grand Ballroom G
1:30 PM Designed in Texas Physical Design II Hall 5
1:30 PM Designer Track Back-End Flows and Methodologies 18C
1:30 PM Technical Panels I Blew My Power Budget: Whom Should I Throw Under the Bus? 16AB
1:30 PM Special Sessions Balancing Security and Utility in Medical Devices 12AB
1:30 PM Paper Sessions Teaching the Old Backend Compiler Dog New Tricks 11AB
1:30 PM Paper Sessions Answers to Some of Your Embedded System Design Questions 13AB
1:30 PM Paper Sessions Don't Fret About Your FinFet: Physical Design in 14nm and Beyond 14
1:30 PM Paper Sessions Taming the Beast: Coping with Imperfect Design and Silicon Defects 15
1:30 PM Pavilion Panels Organizational and Management Solutions to the Verification Crisis Booth 509
3:00 PM Global Forum Global Forum Booth 137
3:00 PM Pavilion Panels Is This the Right Time to Create Standards for 2.5D/3D-IC Designs? Booth 509
4:00 PM Designed in Texas Design Methodologies from ESL to Fault-Tolerance Hall 5
4:00 PM Designer Track New Uses of Formal Methods 18C
4:00 PM Technical Panels Is Security the Next Design Dimension? 16AB
4:00 PM Special Sessions The Silicon Flashlight: Mapping the Road to 6nm 12AB
4:00 PM Paper Sessions Better to be Proactive or be a Slacker in NoC Design? 11AB
4:00 PM Paper Sessions Off-the-Shelf Techniques for Quantum and Bio Circuits 13AB
4:00 PM Paper Sessions Enlarging the Universe: Innovative Exploration for RTL and High-Level Synthesis 14
4:00 PM Paper Sessions Emerging Application-Oriented, Low-Power Techniques 15
4:00 PM Pavilion Panels Hardware-Assisted Development in 10 Years: More Need, More Speed Booth 509
6:00 PM Networking Tuesday Reception Outside Ballrooms ABC
7:00 PM Additional Meetings ACM/SIGDA Member Meeting with Ph.D Forum & A. Richard Newton Young Student Fellowship Poster Session Ballroom D
7:00 PM Additional Meetings Birds-Of-A-Feather Meetings Various
7:00 PM Additional Meetings Birds-Of-A-Feather Meeting: Examining the IP Protection P1735 Standard
7:00 PM Additional Meetings Birds-Of-A-Feather Meeting: Creating a Standard for Interoperability of Multi-language Verification Environments and Components


Wednesday, June 05

TimeTypeTitleLocation
9:00 AM Designed in Texas FPGAs, APUs, and Automotive Microcontrollers Hall 5
9:00 AM Designer Track System Power Estimation and Performance Verification 18C
9:00 AM Technical Panels Disruptive Verification Technologies: Can They Really Make a Difference? 16AB
9:00 AM Special Sessions The Past, Present, and Future of EDA: A Celebration of 50 Years of DAC 12AB
9:00 AM Paper Sessions Huff and PUF 11AB
9:00 AM Paper Sessions Secrets of Analog Verification 13AB
9:00 AM Paper Sessions Litho is Hot! 14
9:00 AM Paper Sessions Understanding Mother Nature and Taming its Wrath 15
9:00 AM Colocated Conferences CELUG/EDAC Enterprise Licensing Conference 10AB
9:00 AM Insight Presentations A Formal Approach to Low-Power Verification 18D
9:15 AM Pavilion Panels EDA 2020: A Pure Vision Booth 509
10:30 AM Pavilion Panels IP Pitfalls: Avoid the Wild Ride Booth 509
11:25 AM Keynotes Designing Mobile Communications SoCs: Handhelds to Infrastructure Ballroom ABC
12:00 PM Designer Track Poster Session 2 Hall 5
12:15 PM Global Forum Global Forum Booth 137
1:30 PM Designer Track Simulation and Emulation 18C
1:30 PM Designer Track Panel: Designer Keynote Q/A Hall 5
1:30 PM Technical Panels Test/Diagnose/Debug: Let the 3D-IC Chaos Begin 16AB
1:30 PM Special Sessions The Future of Operating Systems for Embedded Systems and Software (ESS) 12AB
1:30 PM Paper Sessions Captcha the Chip! 11AB
1:30 PM Paper Sessions Multi Challenges of Embedded Multi-Processing 13AB
1:30 PM Paper Sessions Accelerated Simulation and Verification for Power Grid and Memory 14
1:30 PM Paper Sessions We're Gonna Route Around the Clock 15
1:30 PM Pavilion Panels Learn the Secrets of Design for Yield Booth 509
2:00 PM Insight Presentations Wireless Algorithm Validation from System to RTL to Test 17AB
2:00 PM Insight Presentations Reducing Design and Debug Time with Synthesizable TLM 9ABC
2:30 PM Pavilion Panels Teens Talk Tech Booth 509
3:00 PM Global Forum Global Forum Booth 137
4:00 PM Designed in Texas High-Performance Processors and SoCs Hall 5
4:00 PM Designer Track Physical Design and Manufacturability 18C
4:00 PM Technical Panels EDA: Meet Analytics; Analytics: Meet EDA 16AB
4:00 PM Special Sessions Electronics and Software on Wheels: Embedded Systems Design Challenges for Electric Vehicles and the Path Ahead 12AB
4:00 PM Paper Sessions Adventures in Time and Space: Targeting Resiliency 11AB
4:00 PM Paper Sessions New Frontiers in EDA: From Beyond CMOS to More than Moore 13AB
4:00 PM Paper Sessions Novel Application Scenarios for DVFS Techniques 14
4:00 PM Paper Sessions Verification: from SystemC to the Reality of Silicon 15
6:00 PM Work-In-Progress Work-in-Progress Poster Session Ballroom D
6:00 PM Networking Work-In-Progress Poster Session & Reception Outside Ballroom D
7:30 PM Networking 50th Anniversary Banquet Four Seasons Hotel - Ballroom CD


Thursday, June 06

TimeTypeTitleLocation
9:00 AM Designer Track Physical Design for Memory Design and New Technologies 18C
9:00 AM Designer Track Analog and Physical Issues in the Front End 17AB
9:00 AM Technical Panels Barriers to the Internet of Things: Embedded Software, Security, Cost, Power? 16AB
9:00 AM Special Sessions The Future is Here: Live Demos of the “Next” Transistor 12AB
9:00 AM Paper Sessions System Compilation for Multi-Cores: Analysis and Synthesis 11AB
9:00 AM Paper Sessions Embedded: When Applications and Architectures Collide 13AB
9:00 AM Special Sessions 3D-IC Design: Where Are We Going from Here? 14
9:00 AM Paper Sessions SPICE up the Analysis!! 15
9:00 AM Training Track 1, Part I - SystemVerilog Design: Synthesis-Friendly SystemVerilog 4ABC
9:00 AM Training Track 2, Part I - SystemVerilog Verification: Hardcore SystemVerilog for Class-Based Verification 8ABC
9:00 AM Training Track 3, Part I - ARM Accredited Engineer Program: Kick Start to the ARM (®) Cortex (TM) Family of Processors 6AB
9:00 AM Training Track 4, Part I - ESL and SystemC - The Definitive Guide to SystemC: The SystemC Language 18D
9:00 AM Colocated Conferences Southwest Design For Test Conference 9ABC
11:00 AM Visionary Talk VISIONARY TALK: Kathryn Kranen - President and Chief Executive Officer, Jasper Design Automation, Inc. Ballroom ABC
11:20 AM Keynotes DAC Best Paper Awards and Keynote: "Crystal Ball: From Transistors to the Smart Earth" Ballroom ABC
1:30 PM Designer Track Virtual Platforms and Prototyping 18C
1:30 PM Designer Track Physical Synthesis Tools and Techniques 17AB
1:30 PM Technical Panels Analog Design with FinFETs: “The Gods Must be Crazy!” 16AB
1:30 PM Special Sessions FPGAs as General-Purpose Processors: Progress and Challenges 12AB
1:30 PM Paper Sessions Keeping Austin Weird DAC-Style: Wilder and Crazier Ideas 11AB
1:30 PM Paper Sessions Predicting the Future: Hiding the Memory Bottleneck with Predictable Caches and Scratchpads 13AB
1:30 PM Paper Sessions One Small Step for Placement, One Big Leap for Routability! 14
1:30 PM Paper Sessions From Classical to Novel EDA Systems 15
2:00 PM Training Track 1, Part II - SystemVerilog Design: A Hardware Designers Guide to SystemVerilog Verification 4ABC
2:00 PM Training Track 2, Part II - SystemVerilog Verification: Getting Started with UVM, the Universal Verification Methodology 8ABC
2:00 PM Training Track 3, Part II - ARM Accredited Engineer Program: Software Development for the ARM (®) Cortex (TM) Family of Processors 6AB
2:00 PM Training Track 4, Part II - ESL and SystemC -The Definitive Guide to SystemC: TLM-2.0 and the IEEE 1666-2011 Standard 18D
3:30 PM Designer Track Power and Performance 18C
3:30 PM Designer Track Interconnect Simulation and Analysis 17AB
3:30 PM Technical Panels Cyber-Physical System Software: Emperor’s New Clothes or Not? 16AB
3:30 PM Special Sessions Powering Heterogeneous SoCs at the Right Place and Right Time 12AB
3:30 PM Paper Sessions Age of Flash 11AB
3:30 PM Paper Sessions Why Does Constraint-Driven Design Matter for Multicore Embedded Systems? 13AB
3:30 PM Paper Sessions System Design with Power and Thermal Constraints 14
3:30 PM Paper Sessions Got Yield Problems? Take a Closer Look at Variability and Reliability! 15
5:30 PM Networking Networking Reception Outside Room 11AB


Friday, June 07

TimeTypeTitleLocation
8:00 AM Additional Meetings International Workshop on Logic and Synthesis (IWLS) Courtyard Austin Downtown/ Convention Center


Design Automation Conference Sponsors IEEE Solid State Circuits Society Electronic Design Automation Consortium CEDA - IEEE Council on Electronic Design Automation SIGDA Special Interest Group - Design Automation