SESSION 33: SKY TALKS
21st Century Digital Design Tools
Wednesday, June 5, 2013
Time: 2:30 PM — 3:00 PM
|Moderator: ||Soha Hassoun - Tufts Univ., Medford, MA|
Most chips today are designed with 20th century CAD tools. These tools, and the abstractions they are based on, were originally designed to handle designs of one million gates or less. They are not up to the task of handling today's billion gate designs. The result is months of delay and considerable labor from final RTL to tapeout. Surprises in timing closure and power consumption are common. Even taking an existing design to a new process node is a time-consuming and laborious process.
21st century CAD tools should be based on higher-level abstractions to enable billion gate chips to go from final RTL to tapeout in days, not months. Key to attaining this increase in productivity is raising the level of design and using simple, standard interfaces. Designs should be composed from high-level modules - processors, modems, codecs, memory subsystems, and I/O subsystems - rather than gates and flip-flops. Each module, which we expect to contain 105 gates or more, is placed as a unit, and communicates over a standard NoC. Restricting modules to standard sizes and aspect ratios further simplifies physical design. We expect even a large chip to contain at most a few thousand such modules and expect the physical design of such a chip to take a few days with minimal labor (after the modules are complete).
is Chief Scientist and Senior Vice President of Research at NVIDIA and a Professor of Computer Science and Electrical Engineering at Stanford University.
Dally first joined NVIDIA in 2009 after spending 12 years at Stanford University, where he was chairman of the computer science department and the Willard R. and Inez Kerr Bell Professor of Engineering. Dally and his Stanford team developed the system architecture, network architecture, signaling, routing and synchronization technology that is found in most large parallel computers today.
Dally was previously at the Massachusetts Institute of Technology from 1986 to 1997, where he and his team built the J-Machine and M-Machine, experimental parallel computer systems that pioneered the separation of mechanism from programming models and demonstrated very low overhead synchronization and communication mechanisms. From 1983 to 1986, he was at the California Institute of Technology (Caltech), where he designed the MOSSIM Simulation Engine and the Torus Routing chip, which pioneered wormhole routing and virtual-channel flow control.
Dally is a cofounder of Velio Communications and Stream Processors. He is a member of the National Academy of Engineering, a Fellow of the American Academy of Arts & Sciences, a Fellow of the IEEE and the ACM. He received the 2010 Eckert-Mauchly Award, considered the highest prize in computer architecture, as well as the 2004 IEEE Computer Society Seymour Cray Computer Engineering Award and the 2000 ACM Maurice Wilkes Award. He has published more than 200 papers, holds more than 75 issued patents and is the author of two textbooks, “Digital Systems Engineering” and “Principles and Practices of Interconnection Networks.”
Dally received a bachelor’s degree in electrical engineering from Virginia Tech, a master’s degree in electrical engineering from Stanford University and a PhD in computer science from Caltech.
21st Century Digital Design Tools
|Speaker: ||William J. Dally - NVIDIA Corp., Stanford Univ., Santa Clara, CA|
|Authors: ||William J. Dally - NVIDIA Corp., Stanford Univ., Santa Clara, CA|
| ||Chris Malachowsky - NVIDIA Corp., Santa Clara, CA|
| ||Stephen W. Keckler - NVIDIA Corp., Univ. of Texas at Austin, Santa Clara, CA|