Track 1, Part I - SystemVerilog Design: Synthesis-Friendly SystemVerilog
Thursday, June 6, 2013
Time: 9:00 AM — 12:30 PM
Verification and simulation
|Organizer: ||Lori Sanine - Doulos, San Jose, CA|
|Speaker: ||Doug Smith - Doulos, Austin, TX|
(Includes a 30-minute coffee break)
Over the past few years SystemVerilog has risen to become the dominant language for constrained random hardware verification, but at the same time SystemVerilog has a lot to offer the hardware designer. SystemVerilog includes a number of significant improvements over Verilog which can be exploited by hardware designers to make their code more concise and readable.
This session will teach you how to use the SystemVerilog language for hardware design by focusing on the parts of the SystemVerilog language that are widely supported by commercial RTL synthesis tools. This session is aimed at engineers who are currently using Verilog or VHDL for RTL design, and who want to start taking advantage of the power of SystemVerilog to better express their hardware design intent.
This track is taught by Doug Smith, Doulos Senior Member, Technical Staff, who has wide experience of teaching SystemVerilog.