Track 1, Part II - SystemVerilog Design: A Hardware Designers Guide to SystemVerilog Verification
Thursday, June 6, 2013
Time: 2:00 PM — 5:30 PM
Verification and simulation
|Organizer: ||Lori Sanine - Doulos, San Jose, CA|
|Speaker: ||Doug Smith - Doulos, Austin, TX|
(Includes a 30-minute coffee break)
SystemVerilog has come to its current dominant position because of its strength as a verification language, but the successful application of SystemVerilog for verification depends in part on the ability of the hardware designer to understand the needs of the verification engineer, and the learning curve for hardware designers starting to use SystemVerilog for verification can be very steep.
This session will introduce some of the verification features of the SystemVerilog language with a particular focus on the needs of the hardware designer, and is aimed at designers who are currently using Verilog or VHDL. We will teach the use of SystemVerilog Assertions to capture design intent, and will introduce some of the SystemVerilog language features needed for randomizing stimulus, checking, and collecting functional coverage information.
This track is taught by Doug Smith, Doulos Senior Member, Technical Staff, who has wide experience of teaching SystemVerilog.