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EDA1. System-Level Design & Codesign
EDA1.1 System specification, modeling, analysis, simulation, verification, and performance analysis
EDA1.2 Scheduling, HW/SW partitioning, HW/SW interface synthesis
EDA1.3 IP and platform-based design
EDA1.4 Security and IP protection
EDA1.5 Design of Multiprocessor System-On-Chip (MPSOC) and case studies
EDA1.6 Application-specific processor design tools
EDA2. System-Level Communication and Networks-on-Chip
EDA2.1 Modeling and performance analysis
EDA2.2 Communications-based design, communication and network synthesis
EDA2.3 Optimization for energy, fault tolerance, reliability
EDA2.4 Interfacing and software issues, beyond-the-die communication
EDA2.5 NoC design methodologies, case studies and prototyping
EDA3. Power Analysis and Low-Power Design
EDA3.1 System-level power design and thermal management
EDA3.2 System/Architectural low-power techniques: partitioning, scheduling, and resource management
EDA3.3 High-level power estimation and optimization
EDA3.4 Gate-level power analysis and optimization
EDA3.5 Device and circuit techniques for low-power design
EDA3.6 Power-aware and energy-efficient wireless protocols, algorithms and design techniques
EDA4. Verification
EDA4.1 Functional, transaction-level, RTL, and gate-level modeling and verification of hardware design
EDA4.2 Dynamic simulation, equivalence checking, formal (and semiformal) verification model and property checking
EDA4.3 Emulation and hardware simulators or accelerator engines
EDA4.4 Modeling languages and related formalisms, verification plan development and implementation
EDA4.5 Assertion-based verification, coverage analysis, constrained random testbench generation
EDA5. High-Level Synthesis, Logic Synthesis, and FPGAs
EDA5.1 Combinational, sequential and asynchronous logic synthesis
EDA5.2 Library mapping, cell-based design and optimization
EDA5.3 Interactions between logic design and layout or physical synthesis
EDA5.4 High-level, behavioral, algorithmic, and architectural synthesis, "C" to gates tools and methods
EDA5.5 Resource scheduling, allocation, and synthesis
EDA5.6 Logic synthesis and physical design techniques for FPGAs
EDA5.7 Configurable and reconfigurable computing
EDA6. Analog Design and Simulation
EDA6.1 Analog, mixed-signal, and RF design methodologies
EDA6.2 Automated synthesis and optimization of analog designs
EDA6.3 Analog, mixed-signal, and RF simulation
EDA6.4 High-frequency and electromagnetic simulation
EDA6.5 Model order reduction techniques for analog/RF designs
EDA6.6 Substrate noise simulation for analog/RF designs
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EDA7. Physical Design and Design Closure
EDA7.1 Floorplanning, partitioning, placement
EDA7.2 Buffer insertion and interconnect planning
EDA7.3 Routing and congestion analysis
EDA7.4 Transistor and gate sizing, local physical synthesis
EDA7.5 Clock network synthesis
EDA7.6 Physical verification and design rule checking
EDA7.7 Physical design of 3-D integrated circuits
EDA7.8 Reticle enhancement, lithography-related design optimizations
EDA8. Analysis of Digital Design
EDA8.1 Deterministic and statistical timing analysis
EDA8.2 Electrical simulation, delay modeling and library characterization
EDA8.3 Electrical and thermal reliability, electrical-thermal simulation
EDA8.4 Power delivery analysis and reduction
EDA8.5 Signal integrity and crosstalk modeling
EDA8.6 Process technology characterization, BEOL extraction, and modeling
EDA8.7 Timing and signal/power integrity analysis of 3-D ICs
EDA8.8 Novel clocking methodologies
EDA9. Test and Reliability
EDA9.1 Test quality/reliability, current based test, delay test, low-power test
EDA9.2 Digital fault modeling, ATPG, DFT, BIST, compression
EDA9.3 Memory / FPGA test and repair
EDA9.4 Fault-tolerance and online testing
EDA9.5 Analog/mixed-signal/RF testing
EDA9.6 Board- and system-level test, system-on-chip (SOC) testing
EDA9.7 Silicon debug and diagnosis, post-silicon design validation
EDA9.8 Soft errors
EDA9.9 Design for resilience under manufacturing variations
EDA9.10 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
EDA9.11 Testing of 3-D ICs
EDA10. New and Emerging Design Technologies (including but not restricted to)
EDA10.1 New transistor structures, devices, and novel process technologies
EDA10.2 Nanotechnologies, nanowires, nanotubes
EDA10.3 Optical devices and communication
EDA10.4 Quantum computing
EDA10.5 Biologically-based or biologically-inspired computing systems
EDA10.6 MEMS, sensors, actuators, imaging devices
EDA10.7 Design Automation for System & Synthetic Biology
EDA11. Electronic Design Automation (EDA) Wild and Crazy Ideas (WACI)
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