2021 SkyTalk Speakers

View the Entire 2021 Conference Program

William Chappell, CTO, Azure Global 

William ChappellCloud & AI Technologies for Faster, Secure Semiconductor Supply Chains

Monday, December 6, 2021 | 1:00 PM - 1:45 PM

Semiconductors are deeply embedded in every aspect of our lives, and recent security threats and global supply chain challenges have put a spotlight on the industry. Significant investments are being made both by nation states and commercial industry, to manage supply chain dependencies, ensure integrity and build secure, collaborative environments to foster growth. These shifts provide unique opportunities for our industry. This talk blends insights and experiences from government initiatives and Azure's Special Capabilities & Infrastructure programs, to outline how Cloud + AI technologies, along with tool vendors, fabless semiconductor companies, IP providers, foundries, equipment manufacturers and other ecosystem stakeholders can contribute to building a robust, end-to-end, secure silicon supply chain for both commercial and government applications, while generating value for their businesses.


Dr. William Chappell is the CTO of Azure Global. He is currently bootstrapping efforts for Microsoft in Space, Critical Infrastructure, and Secure Hardware Design. He was formerly the director of the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office (MTO). Serving in this position, he focused the office on three key thrusts important to National Security. These thrusts included ensuring unfettered use of the electromagnetic spectrum, building an alternative business model for acquiring advanced DoD electronics that feature built-in trust, and developing circuit architectures for next-generation machine learning. He created and kicked off the Electronics Resurgence Initiative (ERI), the nation’s largest investment in the foundation of electronics. Also, as office director, he helped structure and authorize the Spectrum Collaboration Challenge (SC2), the first DARPA RF grand challenge, continuing his focus on adaptive and collaborative RF systems. As a program manager at DARPA, he led efforts on adaptive and high-performance RF systems. He developed the arrays at commercial timescales (ACT) and managed the Adaptive RF Technologies (ART) portfolio. These activities led to next generation RF components and systems, such as the RF FPGA, and ultra-high-speed digitizers for direct RF sampling. Prior to his DARPA appointment, Dr. Chappell served as a professor in the Electrical and Computer Engineering Department of Purdue University, where he led the Integrated Design of Electromagnetically Applied Systems (IDEAS) Laboratory. Dr. Chappell’s research focused on high-frequency components, specifically the unique integration of RF and microwave components based on electromagnetic analysis. Dr. Chappell is the recipient of numerous research and teaching awards. He received his Bachelor of Science (summa cum laude), Master of Science, and Doctor of Philosophy degrees in Electrical Engineering, all from the University of Michigan.

Kailash Gopalakrishnan, IBM Fellow and Sr. Manager, Accelerator Architectures and Machine Learning

Kailash GopalakrishnanThe precision scaling powered performance roadmap for AI Inference and Training systems​

Tuesday, December 7, 2021 | 1:00 PM - 1:45 PM

Over the past decade, Deep Neural Network (DNN) workloads have dramatically increased the computational requirements of AI Training and Inference systems - significantly outpacing the performance gains obtained traditionally using Moore's law of silicon scaling. New computer architectures, powered by low precision arithmetic engines (FP16 for training and INT8 for Inference), have laid the foundation for high performance AI systems - however, there remains an insatiable desire for AI compute with much higher power-efficiency and performance. In this talk, I'll outline some of the exciting innovations as well as key technical challenges - that can enable systems with aggressively scaled precision for inference and training, while fully preserving model fidelity. I'll also highlight some key complementary trends, including 3D stacking, sparsity and analog computing, that can enable dramatic growth in the AI system capabilities over the next decade. 


Kailash Gopalakrishnan is an IBM Fellow and a senior manager of the accelerator architectures and machine learning group at the IBM T. J. Watson Research Center, where he has worked in the areas of computer architecture, deep learning, semiconductor devices, circuit design and emerging memory devices. Over the past decade, his primary research has centered around the invention and development of specialized platforms that have dramatically improved industry-wide AI systems’ performance and revolutionized the incorporation of AI capabilities within IBM Systems. He has a Ph.D. in Electrical Engineering from Stanford University and his current research interests include accelerator microarchitectures, machine learning and approximate computing.



Sam Naffziger, AMD Senior Vice President, Corporate Fellow, and Product Technology Architect, AMD

Sam Naffziger Cross-Disciplinary innovations Required for the Future of Computing

Wednesday, December 8, 2021 | 1:00 PM - 1:45 PM

With traditional drivers of compute performance a thing of the past, innovative engineers are tapping into new vectors of improvement to meet the world's demand for computation. Like never before, the future of computing will be owned by those who can optimize across the previously siloed domains of silicon design, processor architecture, package technology and software algorithms to deliver performance gains with new capabilities. These approaches will derive performance and power efficiency through tailoring of the architecture to particular workloads and market segments, leveraging the much greater performance/Watt and performance/area of accelerated solutions. Designing and verifying multiple tailored solutions for markets where a less efficient general purpose design formerly sufficed can be accomplished through modular architectures using 2.5D and 3D packaging approaches. Delivering on modular solutions for high volume markets requires simultaneously optimizing across packaging, silicon, interconnect technologies where in the past, silicon design was sufficient. This talk will cover these trends with the vectors of innovation required to deliver these next generation compute platforms.


Samuel Naffziger is AMD senior vice president, Corporate Fellow, and Product Technology Architect. Naffziger works across the company to optimize product technology choices and deployment with a continued focus on driving best practice power/performance/area methodology to maximize product competitiveness, efficiency, and cost. Naffziger has been the lead innovator behind many of AMD’s low-power features and chiplet architecture. He has over 32 years of industry experience with a background in microprocessors and circuit design at Hewlett Packard, Intel and AMD. Naffziger received a Bachelor of Science degree in Electrical Engineering from the California Institute of Technology (CalTech) and a Master of Science from Stanford. Naffziger holds more than 130 U.S. patents in the field and authored dozens of publications and presentations on processors, architecture and power management. He is an IEEE Fellow.