WORK-IN-PROGRESS POSTERS

DAC Work-in-Progress (WIP) aims to provide authors an opportunity to receive early feedback on current work and preliminary results. WIP submissions will be presented at a poster session where the WIP poster presenters will showcase their work and get timely feedback from professionals including academia, EDA industries, designers, and makers.


TIMELINE

  • October 1, 2020: Submission site open.
  • January 20, 2021: Submission deadline.
  • March 17, 2021: Notification - Accept as poster, accept as presentation, or reject notifications will be emailed to authors.
  • March 24, 2021: Confirmation Forms Due - Accepted posters must submit a confirmation form.
  • June 1, 2021: Final Files - Deadline for authors to submit PDF of final poster.

POSTER GUIDELINES

WIP presenters are required to present a poster describing their work (see below for poster guidelines) during the designated WIP session and be available for the entire hour to discuss their work with interested attendees. This provides an opportunity for extended discussion with interested members of the audience.

Each author is allocated a 42” tall x 36” wide area for a poster.  Poster sessions will run for one hour, and may include 20-30 posters. Poster authors are welcome to distribute additional material to interested attendees at the poster session. Such material can include extended abstracts and whitepapers. 

  • One poster board is allocated to each presentation.  
  • Posters must be mounted using push pins provided by the organizing committee.
  • The title of your poster should be done in block letters which are AT LEAST 8 to 10 cm (3 to 4 inches) high.
  • All text must be easily readable from a distance of 1 to 2 meters. Make the lettering at least 1 cm high, smaller lettering will not be legible from a distance of 1 to 2 meters.
  • All graphs and charts should be AT LEAST 25 X 30 cm (approximately 8.5 x 11 inches) or larger.
  • It is a good idea to sequentially number your materials in the poster. This will indicate to the viewer a logical progression through your poster.
  • Provide an introduction (outline) and a summary or conclusion for your poster.
  • Prepare your poster carefully so that it can be used as the basis to explain and answer questions from the viewers.
  • Have your business cards available for those who may wish to contact you at a later date.
  • Bring along a tablet of blank paper that you may use for a discussion of technical details relating to your poster.

SUBMISSION FORMAT

Authors are asked to submit a 100 word abstract or a one-page manuscript. Submission should clearly specify a technical problem being targeted, outline a solution, and provide some early results. Submissions that are accepted to the WIP program are required to have one author register for the conference and present a poster in the DAC WIP session.

The accepted WIP authors are expected to submit a poster after notification. A 100-word summary abstract will be published on the DAC website, but the submission will not be included in the official DAC proceedings so that the authors can re-submit their complete work to future DAC and other conferences and journals.

WIP submissions require the following:

  • Title
  • Abstract (approximately 100 words) or a page manuscript (uploaded as a PDF file)
  • List of all co-authors (including Affiliation, City, State, Country, and Email for each person)

Authors are responsible for ensuring that their manuscript meets the submission guidelines. There will be no re-submissions to correct any issues.

SUBMISSION TIMELINE

  • Abstract and Manuscript Deadline - March 12, 2021

SUBMISSION RULES (ABSTRACT & MANUSCRIPT)

  • Submitter must enter names, affiliations, city, state, country and email address of ALL co-authors. The addition of new co-authors will not be permitted after March 12, 2021.
  • DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)’ own previous work or affiliations in the bibliographic citations being in the third person. Avoid the use of “omitted for blind review” in the bibliography section.
  • The abstract of approximately 100 words must clearly state the significant contribution, impact, and results of the manuscript.
  • An author of each accepted WIP submission is required to:
    • Produce a poster following the instructions provided.
    • Sign and submit an AV Permission and Release form.

In addition:

  • One co-author on the presentation is required to pay the Speaker Registration Fee.
  • The speaker must present the poster at the conference.

SUBMISSION CATEGORIES

Authors of WIP poster submissions are required to specify a category from the list below. Authors of submissions that cover cross-cutting topics (e.g. low-power, multi-core architecture, 3-D, emerging technologies, IoT, etc.) should select a category that is closest to the essential contribution of the submission. Authors may choose a second submission category to accommodate cross-cutting contributions. Your selection should be based on the consideration of which expertise group of people would better review your submissions.

EDA

EDA1. System-on-Chip Design Methodology

  • EDA1.1 System-on-Chip (SoC) specification, modeling, analysis, simulation, and verification
  • EDA1.2 Application-specific processor design tools
  • EDA1.3 Design tools for accelerator-rich architectures and heterogeneous multi-cores
  • EDA1.4 Tools for reconfigurable computing
  • EDA1.5 HW/SW co-design, interface synthesis, and co-verification
  • EDA1.6 System-level methods for reliability and aging

EDA2. In-Package and On-Chip Communication and Networks-on-Chip

  • EDA2.1 Communication architecture modeling and analysis
  • EDA2.2 Synthesis and optimization of communication architectures
  • EDA2.3 NoC architectures and design methodologies
  • EDA2.4 Communication architectures using alternative technologies (e.g., nanophotonics, RF, 3D, etc.)

EDA3. Cross-Layer Power Analysis and Low-Power Design

  • EDA3.1 System-level low-power design analysis and management
  • EDA3.2 Architectural power reduction techniques and analysis tools
  • EDA3.3 Low-power circuit design methods and tools
  • EDA3.4 System-level and architectural thermal analysis and management

EDA4. RTL/Logic Level and High-level Synthesis 

  • EDA4.1 Combinational, sequential and asynchronous logic synthesis
  • EDA4.2 Technology mapping, cell-based design and optimization
  • EDA4.3 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods
  • EDA4.4 Synthesis for FPGAs
  • EDA4.5 Synthesis for circuits in emerging device technologies

EDA5. Analog Design, Simulation, Verification and Test

  • EDA5.1 Analog, mixed-signal, and RF design methodologies
  • EDA5.2 Automated synthesis and optimization of analog designs
  • EDA5.3 Analog, mixed-signal, RF, electromagnetic, substrate noise modeling and simulation
  • EDA5.4 Model order reduction techniques for analog/RF designs

EDA6. Digital Design, Timing and Simulation

  • EDA6.1 Timing analysis and simulation/delay modeling
  • EDA6.2 Power/signal integrity analysis and simulation
  • EDA6.3 Process technology modeling
  • EDA6.4 Circuit- and gate-level power/thermal analysis

EDA7. Physical Design and Verification, Lithography and DFM

  • EDA7.1 Floorplanning, partitioning, placement
  • EDA7.2 Interconnect and clock network planning and synthesis
  • EDA7.3 Cross-layer placement and routing optimization for timing/power/yield
  • EDA7.4 Post-Layout and post-silicon optimizations
  • EDA7.5 Physical design of 3-D integrated circuits
  • EDA7.6 Reticle enhancement, lithography-related design optimizations and design rule checking
  • EDA7.7 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
  • EDA7.8 Device-, circuit- and gate-level techniques for reliability (e.g.: manufacturing variations, aging, etc.)

EDA8. Design Verification and Validation

  • EDA8.1 Functional and transaction-level modeling and validation, coverage and test generation for hardware and embedded systems
  • EDA 8.2 Emulation and hardware acceleration
  • EDA8.3 Formal and semi-formal verification and verification technologies
  • EDA8.4 Verification of firmware, software, and hybrid hardware/software systems
  • EDA8.5 Machine learning techniques for verification
  • EDA8.6 Post-silicon design validation and debug
  • EDA8.7 Validation of cognitive systems

EDA9. Manufacturing Test and Reliability

  • EDA9.1 Fault modeling, ATPG, DFT, BIST, compression
  • EDA9.2 Memory, FPGA and emerging technology test and reliability
  • EDA9.3 SoC, board- and system-level test
  • EDA9.4 Post-silicon test and defect diagnosis
  • EDA9.5 Analog/mixed-signal/RF verification and test
  • EDA9.6 Noise, aging induced delays, and reliability analysis

DESIGN

DES1. Design of Cyber-physical Systems and IoT

  • DES1.1 Cyber-physical systems and Internet-of-Things (IoT) platforms
  • DES1.2 Low-power and energy-efficient design techniques for IoT
  • DES1.3 Partitioned Edge/hub/cloud processing
  • DES1.4 Dependable and safety-critical embedded system design
  • DES1.5 Networking and storage system design
  • DES1.6 Advanced wireless communication system design

DES2. SoC, Heterogeneous, and Reconfigurable Architectures

  • DES2.1 Architectures for stochastic, statistical and approximate computing
  • DES2.2 SoC and heterogeneous multi- and many-core architectures
  • DES2.3 Run-time and design-time reconfigurable processor architectures 
  • DES2.4: 2.5D/3D heterogeneous integration of compute, memory and communication platforms

DES3. Approximate Computing for AI/ML

  • DES3.1 Approximation techniques for neural network training and inference
  • DES3.2 Application-driven approximations in hardware architecture and design for AI/ML
  • DES3.3 AI/ML architecture-algorithm co-design for approximate computing

DES4. AI/ML System Design

  • DES4.1 Hardware and architecture of AI/ML systems
  • DES4.2 Software and algorithms for AI/ML
  • DES4.3 System level co-design and co-optimizations for AI/ML

DES5. Emerging Models of Computation

  • DES5.1 Biologically-based or biologically-inspired computing systems
  • DES5.2 Design automation for system & synthetic biology
  • DES5.3 Neuromorphic and brain-inspired computing

DES6. Digital and Analog Circuits

  • DES6.1 2.5-D and 3-D integrated circuit designs
  • DES6.2 Clock network and interconnect designs
  • DES6.3 Low-power and energy-efficient digital circuits
  • DES6.4 Analog, mixed-signal and RF circuits
  • DES6.5 Circuits for advanced wireless communication
  • DES6.6 Memory design

DES7. Emerging Device Technologies

  • DES7.1 New transistor structures, beyond-CMOS devices (e.g., steep-slope devices, spintronics), and new process technologies
  • DES7.2 Nanotechnologies, nanowires, nanotubes
  • DES7.3 Emerging non-volatile memory devices

DES8. Quantum Computing

  • DES8.1 Quantum computing applications and algorithms
  • DES8.2 Quantum computing hardware architecture and design
  • DES8.3 Quantum computing technology

ESS

ESS1. Embedded Software

  • ESS1.1 Embedded software verification methodologies
  • ESS1.2 Embedded operating systems, middleware, runtime support, resource management, and virtual machines
  • ESS1.3 Software techniques for multicores, GPUs, and multithreaded embedded architectures
  • ESS1.4 Compilation strategies, code transformation and parallelization techniques for embedded systems
  • ESS1.5 Domain-specific embedded libraries (e.g., for machine learning)
  • ESS1.6 Embedded Software Development Case Studies (e.g., ANDROID development, ARM-based systems, RISC-V based systems etc.)

ESS2. Embedded System Design Methodologies

  • ESS2.1 Embedded system specification, virtual prototyping and simulation
  • ESS2.2 Embedded system synthesis and optimization
  • ESS2.3 Analysis of embedded system QoS metrics - performance, battery life, reliability, etc.
  • ESS2.4 Design methodologies for self-aware, self-adaptive and autonomous embedded systems
  • ESS2.5 Design methodology for mobile, wearable and Internet of Things devices

ESS3. Embedded Memory, Storage and Networking

  • ESS3.1 On-chip memory architectures and management: Scratchpads, compiler controlled memories, etc.
  • ESS3.2 Embedded storage systems organization and management
  • ESS3.3 Memory and Storage hierarchies with emerging memory technologies

ESS4. Near-Memory and In-Memory Computing

  • ESS4.1 Memory architecture and management for emerging memory technologies
  • ESS4.2 Data reorganization engines
  • ESS4.3: In-memory and near-memory computing for AI/ML including neural networks

ESS5 Time-Critical System Design

  • ESS5.1 Real-time analysis and tool flows
  • ESS5.2 WCET methods and tools for embedded hardware/software systems
  • ESS5.3 Mixed-Criticality system design

SECURITY/PRIVACY

SEC1. Hardware Security: Primitives, Architecture, Design & Test

  • SEC1.1 Hardware security primitives for cryptography, key generation, and authentication
  • SEC1.2 Trusted IP and system-on-chip (SoC) design and manufacturing
  • SEC1.3 Emerging technologies (Nanoscale devices, 3D, etc.) and security 
  • SEC1.4 Hardware security verification, validation and test
  • SEC1.5 Post-quantum crypto algorithms and implementations

SEC2. Hardware Security: Attack and Defense

  • SEC2.1 Hardware-enabled side-channel attacks and defenses
  • SEC2.2 Software-driven side-channel attacks and defenses
  • SEC2.3 AI/ML-based attacks and defenses
  • SEC2.4 Adversarial machine learning attacks and defenses
  • SEC2.5 Hardware supply chain protection and anti-counterfeiting
  • SEC2.6 Reverse engineering and hardware obfuscation

SEC3. Embedded and Cross-Layer Security

  • SEC3.1 Embedded software and system-level techniques for security
  • SEC3.2 Architectural support for software and embedded systems security
  • SEC3.3 Cyber-physical systems and IoT security
  • SEC3.4 Embedded security: metrics, models, verification and validation
  • SEC3.5 Machine learning for cyber defense
  • SEC3.6 Security vulnerabilities in artificial intelligence

AUTONOMOUS SYSTEMS (Automotive, Robotics, Drones)

AS1 Autonomous Systems Design Tools and Methodologies

AS2 Autonomous Systems Architectures

AS3 Autonomous Systems Safety and Reliability

IoT

DAC welcomes all papers related to IoT. Depending on the specific topic of the paper, when submitting, submissions should be categorized accordingly i.e. EDA (related to tools and design methodologies), Design (related to accelerating neural networks, etc.)

  • DES1.1 Cyber-physical systems and Internet-of-Things (IoT) platforms

  • DES1.2 Low-power and energy-efficient design techniques for IoT
  • ESS2.5 Design methodology for mobile, wearable and Internet of Things devices
  • SEC3.3 Cyber-physical systems and IoT security

MACHINE LEARNING/AI

DAC welcomes all papers related to Machine Learning and AI. Depending on the specific topic of the paper, when submitting, submissions should be categorized accordingly i.e. EDA (related to tools and design methodologies), Design (related to accelerating neural networks, etc.), etc.

  • EDA8.5 Machine learning techniques for verification
  • EDA8.7 Validation of cognitive systems
  • DES3.1 Approximation techniques for neural network training and inference
  • DES3.2 Application-driven approximations in hardware architecture and design for AI/ML
  • DES3.3 AI/ML architecture-algorithm co-design for approximate computing
  • DES4.1 Hardware and architecture of AI/ML systems
  • DES4.2 Software and algorithms for AI/ML
  • DES4.3 System level co-design and co-optimizations for AI/ML
  • DES5.3 Neuromorphic and brain-inspired computing
  • ESS1.5 Domain-specific embedded libraries (e.g., for machine learning)
  • ESS4.3: In-memory and near-memory computing for AI/ML including neural networks
  • SEC2.3 AI/ML-based attacks and defenses
  • SEC2.4 Adversarial machine learning attacks and defenses
  • SEC3.5 Machine learning for cyber defense
  • SEC3.6 Security vulnerabilities in artificial intelligence

REVIEW PROCESS

  • DAC manuscripts go through a double-blind review process; i.e., the identity of authors and reviewers is only known to the TPC Co-Chairs.
  • DAC ensures that there are no conflicts of interest between authors and reviewers.
  • The duplicate submission rules do not apply to WIP submission since the submission will not be included in the proceedings.

SELECTION PROCESS

The Technical Program Committee (TPC) determines the selection of research manuscripts to be included in the program, as well as their composition into technical sessions within the conference schedule. The TPC will look at the following in selecting manuscripts:

  • Importance of the problem and quality of the technical contribution (design, method, research) described in the manuscript.
  • Originality of the concepts used and described (whether tools, methods or design). Advances over previous approaches should be reflected by describing the significant improvement in the results section. Comparisons with other approaches are also important to justify the advancement claimed in your manuscript.
  • Significance of the results obtained or expected with clues - by measurable quantitative criteria (runtime for tools, optimal results, time for design process steps, simplification or automation of manual effort, etc.).
  • Degree of experimental validation of the concepts. Use in real designs or widely accepted benchmarks with measurable criteria for results is highly desirable, if not essential.
  • A good discussion of limitations of the approach and concepts, and possible areas for future improvement.
  • The quality of manuscript writing, use of English, organization and clarity of presentation.