CONTACT INFORMATION

Ambar Sarkar
Designer/IP Track Program Chair
Email

Natarajan Viswanathan
Designer Track Co-Chair
Email

Monica Farkash 
Designer Track Co-Chair
Email

Randy Fish
IP Track Chair
Email

Mark Kraeling
Embedded Systems Track Chair
Email

Derek Magill
Cloud Focus Chair
Email

SUBMISSION SITE QUESTIONS

Alexis Bauer Kolak
Education Director
Email

Designer Track Presentation Submissions

The DAC Designer Track is the premier forum specifically targeted at design engineers. It brings together IC designers, IP core designers, system developers, automotive electronics engineers, security experts, engineering managers, and verification engineers from across the globe.
 

Hardware designers, software engineers, IP developers, application engineers, and managers/executives from leading companies worldwide will present their experiences on effective design flows, methods, tool usage, as well as IP integration and software development practices. Companies represented in the past include but are not limited to:

  • AMD
  • Cadence
  • Mercedes Benz
  • Qualcomm
  • TSMC
  • ARM
  • Delphi
  • Mentor
  • Samsung
  • Among many other great companies
  • Bosch
  • IBM
  • NVIDIA
  • Synopsis

 

  • BMW
  • Intel
  • NXP
  • TI
 

The Designer Track will include presentations, poster sessions and a rich set of invited talks/panels to facilitate information exchange and interactions. It offers a unique opportunity to network with and learn from other industry experts about best practices and current trends. There is no better way to improve your “design IQ” in such a short amount of time.

The DAC Designer Track committee is looking for submissions that tackle relevant topics and provide high-quality content which target challenges, innovations and trends in chip design, including front-end, back-end, and systems and software design. Also, of interest are submissions addressing unique application requirements and challenges for advanced technologies, automotive, security, machine learning, cloud applications, and IoT.

Whether you are an EDA tool user, hardware designer, software engineer, IP provider, IP core user, application engineer, consultant, or an engineering manager, the Designer Track is an ideal place to meet and share your experiences.


Designer Track Submission Timeline

  • October 1, 2020: Submission site open.
  • January 20, 2021: Submission deadline
  • March 17, 2021: Notification - Accept as poster, accept as presentation, or reject notifications will be emailed to authors.
  • March 24, 2021: Confirmation Forms Due - Accepted posters and presentations must submit a confirmation form.
  • May 15, 2021: Bio & Draft Slides Due - Submission deadline for draft of final posters and/or presentations and speaker bios (for full talks only). All material will be reviewed by Session Chairs.
  • May 22, 2021: Slide Feedback - Deadline for Session Chairs to communicate poster and slide presentation feedback to authors.
  • June 1, 2021: Final Slides and Video Due - Deadline for authors to submit final poster and/or presentation slides and video for the DAC archive.

SUBMISSION GUIDELINES

The following guidelines should be followed when preparing your slides for submission:

  • Submissions are limited to 6 total slides*.
  • Submissions must be in PowerPoint format: 16:9 aspect ratio.
  • Consistent with DAC policy, company logos may appear only on the title slide.
    • Slide 1: Title, author names and affiliations
      • Authors may NOT be added after acceptance, so be sure to list all authors in the initial submission.
    • Slide 2: Motivation
      • Include an introduction that specifies the context and motivation of the submission. Examples: identify challenges associated with the design task at hand, clarify where in the design process the tools are used, and explain why the problem addressed is of interest to the audience.
    • Slide 3: Main Idea
      • Include details on the specific contributions of your work. Examples: innovative use of tools to achieve a specific goal, user enhancements to the tool and/or tool flow, dealing with scalability, details of integrating IP, study of design trade-offs, interfacing with manufacturing.
    • Slide 4: Additional Content Slide
      • Flexibility to add a slide that demonstrates value of the paper/idea
    • Slide 5: Evidence
    • Slide 6: Summary
      • Include a summary that highlights the main results of your work. Results are needed to evaluate the impact of your contribution. Metrics that could be used include productivity enhancement, improved quality of silicon, decreased complexity, and reduced time-to-market.
  • Important: Ensure that you have the necessary legal, trademark, copyright, and/or organizational approval needed to submit your presentation. Take appropriate steps to get this approval early, as the submissions deadline cannot be extended.

*Note: The presentation format described above is what is required for your submission to be reviewed by the Technical Program committee to decide Accept/Reject. The final presentation delivered at DAC will be made up of a Title slide, Author slide and 12 content slides. The expectation is that the final presentation will expand on the submission presentation.

FREQUENTLY ASKED QUESTIONS

What is the Designer Track submission process?

To spare experts from industry the many hours of preparation associated with a regular manuscript submission, Designer Track submissions are in the form of a 6-slide PowerPoint presentation. Authors of the highest quality submissions will be invited to present their work in Designer Track sessions at the conference and a poster on the same subject during a Designer Track poster session. Other authors may also be invited to present a poster during a Designer Track poster session.

Why a Designer Track? How is it different from the Research Track?

The Designer Track is intended specifically for design engineers. Whether you are an EDA tool user, hardware or software designer, application engineer, engineering manager, or a consultant, the Designer Track is an ideal place to meet and share your experiences. This complements DAC’s strong research focus on algorithms and methodology. The Designer Track aims to illustrate benefits and challenges of EDA tool usage, the process of creating successful hardware and software products and/or IP, and to provide educational and networking benefits for both end-users and tool developers. Naturally, the topics cut across hardware (GPU/CPU/SOC/ASIC/FPGA/Memory) and software design, IP and automation, given the rise of highly integrated systems in today’s design projects.

What is the Designer Track submission timeline?

  • October 1, 2020: Submission site open.
  • January 20, 2021: Submission deadline
  • March 10, 2021: Notification - Accept as poster, accept as presentation, or reject notifications will be emailed to authors.
  • March 18, 2021: Confirmation Forms Due - Accepted posters and presentations must submit a confirmation form.
  • April 29, 2021: Speaker Registration Deadline - One author from each presentation must register at the speaker registration rate and present at the conference
  • May 1, 2021: A/V Form Due - Accepted posters and presentations must submit an A/V Permission Form.
  • May 15, 2021: Bio & Draft Slides Due - Submission deadline for draft of final posters and/or presentations and speaker bios (for full talks only). All material will be reviewed by Session Chairs.
  • May 22, 2021: Slide Feedback - Deadline for Session Chairs to communicate poster and slide presentation feedback to authors.
  • June 1, 2021: Final Slides and Video Due - Deadline for authors to submit final poster and/or presentation slides and video for the DAC archive.

For more information, please visit the Designer Track Speaker Resource Center.

Are Designer Track presentations and posters included in the DAC Proceedings?

No. However, Designer Track posters and/or presentation slides will be made available online if the authors give permission. They will be made available on the DAC website after the conference as a part of the DAC Archive.

What kind of submissions from EDA companies make successful Designer Track submissions?

The Designer Track provides an EDA vendor-agnostic and objective forum for designers, IP developers and EDA tool users. To this end, Designer Track submissions that are essentially marketing material from any company will be rejected. On the other hand, joint customer/vendor submissions written from the perspective of the designer/developer are encouraged and are a valuable part of the Designer Track.

Do I have to use a DAC template for my extended abstract?

No. But you are required to follow the submission and formatting guidelines provided on the Designer Track webpage on the DAC website.

May I add an additional author(s) after submission?

No. All authors should be included at submission.

My company’s legal department hasn’t approved my submission yet. Can the deadline be extended?

No. While we sympathize with your situation (many of us have been there), we have a tight schedule and are unable to accommodate late submissions. If your company permits, you may submit your work for review by the DAC technical program committee without such approval. However, you must obtain appropriate legal, copyright, and any other required permissions well-ahead of the deadline for submission of the final presentation and/or poster, if your submission is accepted for presentation in either format. You will not be able to present any work at the Designer Track without suitable permission from your company.

Where do I submit?

All submissions will occur electronically through the DAC website. The submission deadline was January 22, 2021 at 5pm MT (USA).

What does a Designer Track presentation entail?

Authors of accepted presentations will be allocated 15 minutes in a Designer Track session: 13 minutes for the presentation, 1 minute for wrap-up, and 1 minute for Q/A. In addition, presenters are required to present a poster describing their work (see below for poster guidelines) at one of the hour-long Designer Track poster sessions and be available for the entire hour to discuss their work with interested attendees. This provides an opportunity for extended discussion with interested members of the audience.

New for 2021: All accepted presentations are expected to submit a video of their presentation in advance of the event. This does not replace participation in the event. At least one author must attend and present at the live event.

What does a Designer Track poster entail?

Each author is allocated a 42” tall x 36” wide area for a poster. Designer Track poster sessions will run for one hour, and may include 20-30 posters. Poster authors are welcome to distribute additional material to interested attendees at the poster session. Such material can include extended abstracts and whitepapers.

New for 2021: All accepted posters are expected to submit a video of their presentation in advance of the event. This does not replace participation in the event. At least one author must attend and present at the live event.

Please visit the Designer, Embedded Systems and IP Track Poster-Only Presenter Resource Center for more information on presenting during a poster-only session.

What’s the difference between a Designer Track poster and a Designer Track presentation?

Designer Track presentations are oral presentations similar to those in the DAC research track. Designer Track presentations are scheduled in sessions that run parallel to the rest of the DAC program and also include a poster presentation at a Designer Track poster session at the end of the day. If you are selected for a full presentation, you must produce both a slide presentation and a poster for post-session questions and discussion.
Designer Track poster-only presentations must only produce a poster that will be presented during a poster-only session to be held at the end of the day on the exhibit floor for maximum exposure and discussion.

Visit the Poster-Only Presenter Resource Center for questions regarding the production of your poster.

What topics are appropriate for the Designer Track?

We seek a wide variety of contributions from system engineers, hardware designers, IP developers, systems and software developers, application engineers, automotive electronics developers, security experts, IoT experts, and EDA vendor/customer teams. Documented EDA tool use may target electronic design and system design at all levels of abstraction and across all application domains. EDA tool marketing material is strongly discouraged and will be rejected.

How are Designer Track submissions evaluated?


The Designer Track program committee consists of industry experts that collectively represent years of design and software development experience. A good Designer Track presentation addresses innovative tool use coupled with high-quality results. Extra notes are encouraged to be included in the submission. The considerations used by the program committee in acceptance decisions include:

  • Significance of results supported by clear, measurable criteria, including, but not limited to: improved quality of silicon, improved reuse, decreased design process complexity, and reduced time-to-market.
  • Level of innovation in tool use, e.g., utilizing one tool to obtain results that aid another tool, writing scripts to combine tools, user-facing enhancements, intelligent data management. A submission should not mirror the help section in the tool's user manual, but instead address a creative way of using the tool.
  • Ability to overcome design challenges such as scalability, integrating IP, and bridging front-end/back-end gaps.
  • Validation of the proposed techniques using real designs, case studies, or established benchmarks.
  • Discussion of the conceptual limitations of tools and suggestions for future tool improvement. Solid technical contributions should address both the strengths and the weaknesses of the approach.
  • Quality of material including writing, illustrations, and organization.
  • Product marketing material is inappropriate for the Designer Track.

Does the Designer Track have a “Best of” award?

Yes! Best Presentation awards will be selected from the Designer Track. The awards will be based on (a) the quality of the submission, (b) the presentation given at DAC, and (c) the presentation at the poster session. The final selection will be made at the conference by an award committee. The Best Presentation Award will be announced in the DAC general session.

Do Designer Track participants have to register for DAC?

Full DAC conference registrants are automatically allowed to attend the Designer Track. In addition, both Designer Track speakers and any participants who want to attend only the Designer Track sessions, Keynotes, and the Exhibit Floor at DAC can do so at a discounted registration rate via the “Designer Special”  registration package. Please see the DAC registration page for more details.

What should my slide presentation look like?

Remember that your slides must be presented in 13 minutes, plus 1 minute for wrap-up. Presenting meaningful content in a short time is challenging and requires careful thought and planning. Guidelines for preparing your final presentation are provided in the Designer Track Speaker Resource Center. Example presentations from previous years can also be found in the DAC Archives.

My question isn’t answered here! Where can I get an answer?

Please address any unanswered questions to Natarajan Viswanathan, or Monica Farkash, 58th DAC Designer Track Co-Chairs.

Designer Track submissions may describe the overall design and/or application of tools for creating the hardware, IP and/or software components of a novel electronic system. We specifically seek contributions from system engineers, hardware designers, application engineers, and vendor/customer teams. Documented tool use may target electronic design and system design at all levels of abstraction and across all application domains. Regular submissions will be accepted in the following categories:

Front-End Silicon Design (FE)

Front end architecture, design and verification of current day System-on-Chip (SoC) including major components such as CPU, GPU, and DSP. Front end design of entire SoC sub-systems such as graphics, multimedia and modem.

  • FE.01 Architecture Exploration/Design/Optimization of CPU, GPU, DSP, Modem, and Accelerators
  • FE.02 Memory/Bus/Network Architecture/Design
  • FE.03 System and High-Level Hardware Synthesis
  • FE.04 Low-Power Design and Trade-offs
  • FE.05 Design Verification, Test Planning, and Coverage
  • FE.06 Validation, Logic Simulation, Emulation, Hardware Acceleration, FPGAs
  • FE.07 Formal Verification, Linting
  • FE.08 Logic/RTL Synthesis

Back-End Silicon Design (BE)

Back end design and verification of current day SoC, major sub-systems and constituent components (CPU, GPU and DSP). Relevant topics include (and not limited to) physical design, clock tree generation, timing closure, physical verification, and design rule checking.

  • BE.01 Physical Synthesis and Design Techniques and Tools
  • BE.02 Clock Tree and Power Distribution Network Design and Optimization
  • BE.03 Timing and Circuit Analysis and Optimization
  • BE.04 Reliability Analysis and Optimization
  • BE.05 Interconnect Simulation and Analysis
  • BE.06 Timing/Power Sign Off Methodology
  • BE.07 Design for Manufacturing
  • BE.08 Manufacturing Test and Silicon Debug
  • BE.09 Analog, Mixed-Signal, and RF Design
  • BE.10 Custom, Standard Cell, FPGA Design Flows
  • BE.11 3D Silicon Technology and Integration
  • BE.12 Tool Integration, Design Analytics and Methodologies 
  • BE.13 Design Planning/Power Planning/Floorplanning

Automotive

  • AUTO.01 Model-Based Systems and Software Engineering
  • AUTO.02 Seamless Modeling and Simulation Technologies
  • AUTO.03 Safety, Security, and Reliability: Requirements, Tools and Methodology
  • AUTO.04 Automotive E/E Architecture Design
  • AUTO.05 Connectivity and In-Field Software Deployment
  • AUTO.06 Energy-Aware Vehicle Design and Optimization  
  • AUTO.07 Driver Assistance Systems and Highly Automated Driving
  • AUTO.08 Electrified Powertrain and  e-Mobility Solutions

Security

  • SEC.01 Hardware Security: Modeling, Analysis and Synthesis
  • SEC.02 Hardware Security Threats and Metrics
  • SEC.03 Device, Circuit and Architecture Techniques for Security
  • SEC.04 Hardware Security Verification and Validation
  • SEC.05 System-Level Techniques for Security
  • SEC.06 Hardware Support for Software and Security
  • SEC.07 Cross-Layer Security: Modeling, Metrics, Analysis and Synthesis
  • SEC.08 Cross-Layer Security Verification and Validation

IoT

  • IOT.01 Smart Home/Smart Building/Smart City
  • IOT.02 Smart Agriculture
  • IOT.03 Smart Energy Production/Distribution Systems
  • IOT.04 CPS Modeling, Design and Synthesis
  • IOT.05 Smart Health
  • IOT.06 Wearable Circuits, Cyber-Physical Biochips and Low-Power Radio
  • IOT.07 Surveillance and Response Systems
  • IOT.08 Energy Harvesting

Machine Learning

  • ML.01 Machine Learning Techniques for Verification
  • ML.02 Machine Learning Techniques for Logic/RTL Synthesis
  • ML.03 Machine Learning Techniques for Physical Design
  • ML.04 Chip Architectures and Designs Targeting ML/AI Applications
  • ML.05 System Design Targeting ML/AI Applications

Cloud Applications

  • CL.01 Cloud Adoption in Design and Verification Flows
  • CL.02 Case Studies in Cloud Migration
  • CL.03 Cloud Infrastructure for EDA Applications

ADDITIONAL INFORMATION

  • Accepted Designer Track presentations and posters are NOT included in the DAC proceedings. However, accepted Designer Track submissions (both posters and presentation slides) will be made available on the DAC website after the conference as a part of the DAC Archives (subject to approval from the authors).
  • Designer Track submission will be accepted as a 15-minute presentation or presented as a poster in a 60-minute group session.
  • Best Presentation awards will be selected from the Designer Track submissions. The awards will be based on (a) the quality of the submission, (b) the presentation given at DAC, and (c) the presentation at the poster session.