EE Times Presents: The Future of Chiplets
Building Chips for the AI Era
Chiplets, or multi-die systems, present a solution to the insatiable demand for high-performance compute, faster time to market, and custom silicon designs from AI and other fast-growing use cases. They are key to scaling the performance of data centers up and out in a way that keeps power consumption under control, and are thus a key enabling technology on the path to artificial general intelligence.
The EE Times Chiplets in-person conference & Chiplet Pavilion exhibition at DAC 2025 will discuss the progress of chiplet technologies and the chiplet supply chain in all their complexity. The agenda will examine the entire value chain and ecosystem, spanning from initial concept and design exploration to packaging and testing. It will also explore the emergence of initiatives aiming to establish relevant technical standards and a chiplet marketplace.
We will also explore new product directions enabled by 2D and 3D designs, including large- and small-scale multi-die designs, and optical chip-to-chip connectivity.
Presentations will address chiplet standards and technologies, chiplet business models and real-world case studies of chiplet implementations.
Tuesday, June 24
Time: 10:40 AM - 11:25 AM PDT
(CL24-A) The Chiplet Revolution will be Standardized: The New Building Blocks of Computing
These Opening Remarks are presented by Eddie Ramirez, VP of Go-To-Market, Infrastructure Line of Business, Arm.
AI is influencing mulitple workstreams, all of which have different requirements and outcomes. The diversity of these workloads is accelerating the move to custom silicon that is specialized for specific market needs. Chiplets offer a route to composable SoCs without the limitations seen in a typical silicon supply chain. This presentation will review chiplet strategies in play today, and how the market will realize new business models in the future.
Time: 11:25 AM - 11:45 AM PDT
(CL24-B) Verifying 2.5/3D IC Semiconductor Package Connectivity Using Formal Verification
Presented by Mike Walsh, Director of Applications Engineering, Siemens EDA
Integration of multiple ICs in a single package is critical for high performance computing. Due to the huge number of connections after package the ICs, it is hard to verify the correctness of the connections. The traditional way to verify the connections requires a lot of manpower and time and is either not exhaustive or too late in the process. This paper will introduce a new way to verify the package connectivity using formal verification that can exhaustively verify all interconnections between the IC blocks. The flow is automatic for all steps from creating connectivity spec to verify package output connectivity. The automatic parallel algorithms on compute grid can verify huge numbers of connections in minutes even seconds. The script for the flow is simple and only takes a few minutes to setup. Once the script is ready, it can be reused for different package projects.
Time: 11:50 AM - 12:10 PM PDT
(CL24-C) Evolution of HBM (High Bandwidth Memory) in the Chiplet Ecosystem Era
Presented by Archana Cheruliyil, Principal Product Marketing Manager, Alphawave Semi
This presentation will explore the explosive growth in data consumption and how advancements in deep learning are driving transformative changes across industries. As AI applications generate unprecedented data volumes, memory bandwidth and latency challenges become critical hurdles. We will discuss the pivotal role of High Bandwidth Memory (HBM) in overcoming these challenges and unlocking the full potential of next-generation AI hardware through chiplet architectures. The focus will then shift to emerging innovations with HBM4, highlighting the custom implementation of memory chiplet dies using die-to-die (D2D) interfaces. Alphawave Semi's contributions to this evolving memory landscape will be featured, including their in-house HBM4 Controller IP, advanced packaging capabilities, and custom silicon expertise. Finally, we will demonstrate how D2D interfaces for custom HBM chiplets can address the massive data requirements of modern AI workloads, enabling significant performance improvements.
Time: 12:15 PM - 1:15 PM PDT
(CL24-D) Tutorial on 3D Design-for-Test: Wide-Ranging Solutions
This Tutorial is presented by Adam Cron, Distinguished Architect, Synopsys
Design-for-test techniques have been extended using IEEE Std 1838 to support multi-die designs. However, this standard only addresses one of the many test constructs required to fulfil a manufacturing and field test program. In a multi-die development and production environment, large volumes of test data must travel between various sources and the packaged chiplets during the manufacturing process or after deployment to the field. Power, thermal, and bandwidth issues become even more pronounced as dies get stacked in a package, exacerbating multi-die design health issues. Failure to address reliability issues in a single die, die-to-die link, and the entire multi-die design can be costly. Methods leveraging high-speed functional access through standard buses and bandwidth-matching scan access structures are now available to handle the test data volume issues. And several techniques, including sensors and monitors, test, and repair, can be employed to address other multi-die design health issues. This tutorial highlights current test features and new opportunities for future improvements.
Time: 2:00 PM - 2:55 PM PDT
(CL24-E) Panel Discussion: Developing the Chiplet Economy
This Panel Discussion with industry experts is moderated by Nitin Dahad, Editor-in-Chief, EE Times.
The commercial chiplet ecosystem is rapidly evolving, driven by the need for greater scalability, performance, and cost efficiency. However, its growth is challenged by the lack of standardized interfaces, industry-wide collaboration, and the complexity of integrating chiplets from multiple vendors. Ensuring interoperability across different foundries, pre-validating components, and defining clear roles for system integration remain key challenges. Additionally, robust traceability and security mechanisms are critical for managing the multi-die supply chain. This session will explore the readiness of advanced packaging technologies, the role of design tool vendors, silicon makers, and IP providers, and the collaborative efforts required to establish a thriving chiplet economy.
Panelists:
- Abhijeet Chakraborty, VP Engineering, Synopsys
- David Glasco, VP Compute Solutions Group, Cadence
- Nandan Nayampally, Chief Commercial Officer, Baya Systems
- Eddie Ramirez, VP of Marketing and Ecosystem Development, Infrastructure Line of Business, Arm
Time: 3:00 PM - 3:20 PM PDT
(CL24-F) Unleashing Scale Through Chiplets - From Concept to Deployment
Presented by Dr. Sailesh Kumar, Founder and CEO, Baya Systems
From closely coupled processors and accelerators optimized into SoCs and chiplets for edge systems, to data centers pushing scale-up and scale-out barriers with advanced switching, skyrocketing performance demands, especially for AI, the next-generation needs overall system level design mind-set, chiplet-ready thinking and tooling and hyper-efficient, scalable data movement on die and across die. This presentation walks through the state-of art platform and IP solutions to truly unleash the power of chiplets to meet these demands.
Time: 3:25 PM - 3:45 PM PDT
(CL24-G) AI-Driven Early Architecture Explortation for Multi-Die Designs
Presented by Dr. Kamal Desai, Principal Product Manager, Synopsys
Like monolithic SoCs, early architecture exploration is critical for determining performance and power in multi-die designs. Using models for simulating interconnects, memory, and workloads in multi-die designs for early architectural analysis can help designers avoid costly re-spins and accelerate time-to-market. Incorporating AI capabilities to speed up design space exploration and analysis can lead to even higher quality of results and faster turnaround times. This presentation outlines the successful use of AI for pre-RTL multi-die architecture exploration.
Time: 3:50 PM - 4:10 PM PDT
(CL24-H) Cadence SoC Cockpit: Full Spectrum Automation for Chiplet Development
Presented by Dan Slocombe, Design Engineering Architect, Cadence
The semiconductor industry is undergoing a transformation from traditional monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This strategic shift is essential to mitigate complexities associated with scaling designs, optimize yields, and address rising fabrication costs driven by increasing transistor costs. To address these challenges, Cadence is offering a full set of chiplet development solutions, including our new Cadence SoC Cockpit, which aims to streamline and optimize the development of next-generation chiplet and system in package (SiP) designs. Learn about Cadence SoC Cockpit and its use for accelerating SoC designs.
Time: 4:15 PM - 4:35 PM PDT
(CL24-I) Chiplets: Opportunites & Challenges
Presented by Andy Nightingale, VP of Product Management & Marketing and Ashley Stevens, Director of Product Management & Marketing, Arteris
The chiplet revolution is not just a step forward in semiconductor design — it represents a paradigm shift in how we approach performance, scalability, and efficiency in systems, accelerating the capabilities of high-scale applications such as AI, data processing, and more. However, building chiplets today still presents a mosaic of challenges compounded by the lack of de facto interoperability and maturity of industry standards. A key challenge of the chiplet revolution is developing a collaborative ecosystem and exchanging best practices within the industry. This is exactly what we’ll cover. Andy Nightingale and Ashley Stevens of Arteris will give an overview of the opportunities and challenges chiplets create for the industry and share examples of how Arteris' customers approach them.
Time: 4:40 PM - 5:00 PM PDT
(CL24-J) Chiplet Advantages with Ethernet and PCIe Scaling Across Copper and Optics
Presented by Sue Hung Fung, Principal Product Line Manager, Alphawave Semi
As data rates continue to climb and system architectures become increasingly modular, chiplet-based designs are redefining how copper and optical interconnects over Ethernet and PCIe connectivity are deployed. Chiplets enable high-performance, low-power Ethernet interfaces over copper for short-reach links, such as those using Direct Attach Copper (DAC) cables, while also providing flexible pathways to integrate optical transceivers for longer-reach applications. This presentation explores key use cases for chiplets in copper and optical Ethernet, and PCIe environments. It highlights benefits from chiplet partitioning and usage of co-packaged optics (CPO) and near-packaged optics (NPO) architectures. Through examples, we demonstrate how chiplet approaches are crucial for enabling scalable, cost-effective, and future-proof Ethernet and PCIe solutions across a range of network and compute tiers.
Time: 5:05 PM - 5:25 PM PDT
(CL24-K) Multi-Die Signoff - What Designers Need to Know
Presented by Ayhan Mutlu, Senior Architect in Product Engineering, Synopsys
Multi-die designs offer many advantages yet also present several challenges that must be addressed today for future success. One such challenge is signoff, which involves extraction and timing, power, and physical signoff across multiple dies in a single 2.5D or 3D package. It is important to consider signals between dies, interposers, and substrates for static timing analysis, ensuring calculations must account for all the dies within the package. New innovations are required for design rule checking, layout versus schematic verification, and other physical checks. This presentation outlines the key requirements for successful multi-die extraction, timing, power, and physical signoff.
Wednesday, June 25
Time: 10:20 AM - 11:25 AM PDT
(CL25-A) Scaling AI Infrastructure with Optical Chiplets
These Opening Remarks are Presented by Vladimir Stojanovic, CTO and CO-Founder, Ayar Labs.
As AI models grow in size and complexity, the need for scalable compute fabrics has pushed traditional electrical interconnects to their physical and energy limits. Optical I/O chiplets present a disruptive opportunity to break through these barriers, enabling high-bandwidth, low-power communication essential for next-generation AI and HPC systems. This talk presents the architecture, development, and system-level integration of our optical I/O chiplets, designed specifically for scale-up AI fabrics. We explore critical design decisions around photonic/electronic co-packaging, die-to-die interface standards, and system co-design methodologies across silicon, packaging, and interconnect. The talk will also highlight the automation and design tool challenges unique to optical chiplets. Finally, we’ll discuss how chiplet-based optical interconnects are shaping the future of AI compute architectures, and what’s needed from the design automation ecosystem to fully realize their potential.
Time: 11:10 AM - 12:05 PM PDT
(CL25-B) Panel Discussion: Enabling New Design Directions
This Panel Disucssion with INdustry Experts is Moderated by Sally Ward-Foxton, Senior Reporter, EE Times.
Chiplets are redefining design possibilities, enabling breakthroughs in compute and memory integration, heterogeneous architecture, and solutions beyond the reticle limit. This session will explore the evolving industry landscape, the role of advanced design tools in ensuring high-performance chiplet-based systems, and the benefits and limitations of interconnect standards like UCIe and BoW. Key applications and market drivers will be examined. Finally, we will discuss the potential of optical chip-to-chip communication and its implications for the future of high-speed, efficient computing architectures in AI and beyond.
Panelists:
- Ramin Farjadrad, Founding CEO, Eliyan
- Letizia Giuliano, VP of IP Product Marketing and Management, Alphawave Semi
- Ritesh Jain, SVP, Engineering & Operations, Lightmatter
- Vladimiar Stojanovic, CTO and CO-Founder, Ayar Labs
Time: 12:10 PM - 12:30 PM PDT
(CL25-C) Scaling AI Copmute with Next Generation of UCIe Die-to-Die Interface Enabled Chiplets
Presented by Soni Kapoor, Principal Product and Marketing MAnager, Alphawave Semi
As the need for more powerful compute capability continues to grow, the role of chiplets has become increasingly crucial for providing essential scalability and efficiency of next-generation AI infrastructure.
The UCIe (Universal Chiplet Interconnect Express) Die-to-Die (D2D) interface plays a crucial role in enabling low-power and high-speed connectivity between various chiplets within the package. As the demand for higher performance and cost optimization continues to grow, designing UCIe D2D interfaces that cater to a diverse range of packaging options become essential.
This presentation will explore the benefits and challenges of using the D2D interface in 2.5D and 3D package architectures, which is a key enabler for high-performance multi-die System-on-Chip (SoC) in the same package.
We will also discuss how Alphawave Semi is leading the shift to chiplet-based architectures with silicon-proven UCIe D2D IP Subsystems and Chiplets.
Time: 12:35 PM - 12:55 PM PDT
(CL25-D) Unleashing AI Performance: Silicon Photonic INterconnects for the Next Wave of Acceleration
Presented by Eric Yeh, Head of Product Marketing, Lightmatter
As AI workloads continue to scale, both training and inference are driving unprecedented demand for bandwidth, efficiency, and performance at the system level. Conventional interconnect technologies are quickly approaching their limits, making way for a new era powered by silicon photonics. In this presentation, Eric will explore how silicon photonic interconnects are poised to unlock the bandwidth required to support the next generation of AI chips, while simultaneously enabling lower power consumption, longer reach, and dramatically improved AI performance. He will highlight recent innovations from Lightmatter and share a forward-looking perspective on how this transformative technology can meet the growing demands of AI infrastructure, delivering, higher compute efficiency, lower energy per bit, and reduced total cost of ownership. Silicon photonics is no longer a future promise. It's becoming the only viable path to scale AI performance efficiently and sustainably.
Time: 1:00 PM - 1:20 PM PDT
(CL25-E) Advancing Performance in HPC/AI with HBM and IO Solutions
Presented by Kevin Donnelly, VP Strategic Marketing, Eliyan Corporation
AI and HPC systems are being constrained by limitations in the bandwidths of memory and IO connections – the Memory and I/O Walls. The performance of HPC & AI architectures can be improved with higher bandwidth HBM4 and custom HBM memory solutions (including HBM with standard organic packaging), along with advancements in Die-to-Die and Chip-to-Chip connection solutions for advanced packaging and standard packaging.
Time: 1:25 PM - 1:45 PM PDT
(CL-25F) Compound Semiconductor Chiplets in Silicon CMOS - a New Manufacturing Paradigm for Commercial RFICs
Presented by Florian Herrault, CEO, PseudolithIC
PseudolithIC is revolutionizing RFIC design and manufacturing by combining the performance of compound semiconductor transistors such as GaN and InP with the cost, scale, and circuit functionalities of RF silicon CMOS. With a fab-lite model, PseudolithIC has developed a patented chiplet integration and interconnection architecture to maintain high RF and thermal performance while enabling high-volume manufacturing at low cost. Our approach to design and manufacturing will break new grounds in the commercialization of high-performance materials for commercial applications such as 5G/6G communication, satcom applications, or emerging RF systems. In this presentation, we will highlight how our library of digital and physical transistor chiplets sourced from commercial foundries, is changing the design and manufacturing processes for commercial RFICs. Examples of circuit demonstrators operating in the 20-90 GHz range will be presented.
Time: 1:50 PM - 2:10 PM PDT
(CL25-G) Accurate Multi-Physics Verification of Heterogeneous 3D IC Designs
Presented by John Ferguson, Sr Director of Product Management Calibre 3DIC Solutions, Siemens EDA
3D IC design is rapidly becoming a key technique to enable modern electronics designs helping to drive innovations in AI, cloud compute, automotive, military applications and much more. By combining chiplets from heterogeneous processes, it enables new trade-offs in costs, performance, power, and size. But 3D IC design does not come without its own challenges. How can designers combine their chips in such a way to ensure that their meet yields, function as designed and work reliably in the consumer’s use? This presentation will provide an introduction to the solutions available from the Siemens EDA Calibre suite including solutions to check physical verification of multiple heterogeneous chiplets in a package, LVS extraction and comparison to intended circuit behavior, accurate and automated capture of new parasitic effects in the form of TSV or die-to-die coupling, checking of cross-die ESD and other reliability limiting conditions as well as verifying power induced thermal and thermo-mechanical impacts, including their impacts to the electrical circuit behavior. Together these solutions enable designers to capture and monitor impacts early in the design phase, minimizing forced pessimistic decisions through the process, establishing a safe and reliable path towards successful tape-out to product introduction and adoption.
All speaker details can be found here: https://chipletsatdac.eetimes.com/#Speakers