Despite what naysayers have been saying about EDA for several years, there’s a renaissance underway in electronics design. It’s profound, vibrant, exciting and unlike anything we’ve seen in decades. Just ask Dr. William Chappell, director of DARPA’s Microsystems Technology Office (MTO). William and four other DARPA officials came to the 55th Design Automation Conference in San Francisco in June to network and preview ambitious programs to energize design government-industry research and collaboration efforts and silicon and systems design.
The visit came little more than a month before DARPA publicly announced the Electronics Resurgence Initiative (ERI), a massive effort to spend $1.5 billion over the next five years to drive the U.S. electronics industry forward.
We sat down with Chappell in the middle of a crazy-busy DAC to get his thoughts about the state of silicon and system design and design collaboration on the eve of the ERI announcement.
Q: What have you folks been doing in recent years in the context of EDA. There seems to be more DARPA investment coming into EDA and its adjacencies. Andreas Olofsson, former Adapteva CEO and now program manager for your Microsystems Technology Office (MTO), gave a talk at DAC 2018 about the big free silicon compiler DARPA is backing. Can you fill us in?
A: For years we’ve been behind the scenes investing in the basics of electronics. As that’s progressed, we’ve pushed performance. The Department of Defense (DOD) struggled with some design principles as design got harder. Our focus has been lowering the barrier to get new designs out the door, and part of that is EDA.
Q: That’s a big nut to crack. Your output is partly for defense and partly for industry?
A: Primarily, it’s for the defense enterprise but ultimately the entire ecosystem benefits. And we focus on smaller design teams and their challenges. With Andreas Olofsson’s company, for example, we can do 10x better than what a small design team can do. That’s proxy for the size of design teams that often do our designs. So there are incentives there to lower the barriers.
Q: What kind of EDA projects are you working on or considering funding?
A: Well, there’s obviously the silicon compiler work. We’re mainly trying to devise ways that every time you’re doing a design you can somehow capture that information so the next design is easier. It’s using data as the differentiator, as opposed to just human experience. I pay for around 50 tape-outs every two years across the country. They go to a variety of conferences and share their results, but with all those low-level decisions, there’s no way that’s being captured and shared across the community. That would be a huge shift because if you were able to capture that information somehow – we still don’t know how to do it and that’s why it’s a research topic. Then you could pay for everybody in the country to get free silicon access. Capturing that data allows everyone to do better.
That’s at the heart of the IDEA (Intelligence Design of Electronic Assets) program: adding a layer of learning into EDA so it’s capturing the design intent of each of the human designers.
Q: Is there a big element of open source philosophy you’re trying to tap into?
A: We do both. Our goal is to lower the barrier to innovation in this case. We are not set on that being open source or not open source. We’ll explore various pathways in parallel. We’re working with Synopsys, Cadence, Mentor (now Siemens) to lower the barriers, and we’re working with the university community. Some of the base technology that’s required to be put into the hands of people exploring things like adding machine learning (ML) into a design they need more intimate access. You need to be more into the guts of the design. There you’ll see some level of open source. But the goal isn’t to stand up an open-source ecosystem but to get to that final goal: lower barrier to entry.
Q: We are you on the journey?
A: Getting there. Couple of years ago we started with a program called CRAFT (Circuit Realization at Faster Time Scales). We looked at the electronics industry, and we looked at the parallels to the beer industry. You have all this creativity being unleashed in the microbrew world and we said, “what if?” So we hired Linton Salmon to come run it. That’s ending the second of three phases. They looked at a variety of different techniques up front and whittled it down to a couple of design flows. That’s a combination of stuff from the major EDA vendors but also places like Berkeley with the CHISL work. That’s the mid-stream work. Our first foray into this. And then IDEAS: adding a layer of machine learning and POSH (Posh Open Source Hardware) program being the open-source hardware base. That enables a foundation to give SoCs a head start because you have the open source capability. There’s also SSITH (System Security Integration through Hardware and Firmware). It is building a design flow where you have inherent security features built in. So those are four big programs.
Q: Do you sponsor academics?
A: We’re one third academics and two thirds other – defense industry, commercial industry and federal labs.
Q: Even in these four programs?
A: Depends on the program. Most of that has been academic. Cadence and Synopsys are teamed with our defense base on CRAFT. Northrup Grumman, Cadence and Berkeley have been working on CHISL. Berkeley was doing CHISL. Northrup brought the needs statement and design expertise and Cadence provided an ecosystem. The idea was it was that it would be openly available eventually to rest of defense world.
Over the last two years, we’ve opened our doors to commercial relationships in a way we’ve never done before. We do OTAs which are blank-sheet-of-paper contracts. We’re not forcing our government accounting practices in. We have contracts with Arm, Intel, NVDIA, Qualcomm, etc. We’re trying to work with companies we consider the home team and similarly aligned companies.
Q: That falls under the mission that we want to do things more efficiently?
A: Yes, and leverage the commercial world. There’s a lot of complexity. DAC as a conference is working on that. Your community is tapping into that energy and leveraging defense is the way these things are structured.
Q: So you and some colleagues come to DAC frequently, at least in recent years. What do you get from the event?
A: We work directly with academics and industry, and DAC is the place where you can get both under one roof. We’re building an ecosystem and we want to be part of an ecosystem that represents that.
Q: Is there also an urgency now around the problems designers are confronting?
A: Moore’s Law has been amazing, great for the country from an economic as well as the national security perspective. But it’s a double-edged sword. The rising cost of complexity has meant bigger is better. That has unfortunate byproducts with what we’ve been able to do with small design teams. Over time, we’ve used more COTS components. Historically our ability to create ASICs was the best in the world. One reason we unleashed MOSIS was to unleash this creativity in the first place. MOSIS was in response to fabrication difficulties and not wanting everybody to own the design all the way through to fabrication. Breaking those verticals into a stratified design layer. That worked for years as the defense design community was able to extract itself from the fabrication phase and create the world’s best ASICs. Over time that’s become less the case and we have a need to regain that core capability.
Q: The industry disaggregated over 60 years, but there seems to be a re-aggregation in a sense, a virtual sense.
A: We are trying to build communities. That’s one role of government to build communities to go after something larger than any one small entity can do. We don’t try to change commercial forces or the industrial policy. What we will do is to ask to form cross boundaries that might not otherwise exist. Provide a goal to go after and some resources to combine forces.
Q: So your message here is “come work with us?”
A: Next month (July 2018) we’re kicking off the Electronics Resurgence Initiative (ERI). Design is one third of a bigger picture of materials, architecture and design, which is under the umbrella of the Electronics Resurgence Initiative. We’ve announced $1.5 billion in spending in the next five years in those three areas. Design is critical portion of that. But we also want to bring the design community into the discussion on architectures and principal materials development.
We think it’s a very unique inflection point in the industry – the complexity of Moore’s Law mixed with foreign investments that are driving behavior. It’s an interesting time.
We think the investments we are doing are critical for the national defense enterprise. We need to have the world’s best electronics emanate from the United States. The way to do that is to tap into the home team and engineering entities that are headquartered here, working with academics focused on generating that next-generation capability. This is part of a larger national semiconductor plan that is being built right now.
Q: Do you think going forward the relationship between DARPA and the EDA community will grow?
A: We must focus on how we get chips into the field. We believe this community is one of the hearts of where we’re heading. Materials, architecture and design. I don’t want to be biased. We have lots of interests, and architecture and design is very much tied to what you do.