Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference
Thierry Tambe, Harvard University, Cambridge, MA
En-Yu Yang, Harvard University, Cambridge, MA
Zishen Wan, Harvard University, Cambridge, MA
Yuntian Deng, Harvard University, Cambridge, MA
Vijay Janapa Reddi, Harvard University, Cambridge, MA
Alexander Rush, Cornell University, Ithaca, NY
David Brooks, Harvard University, Cambridge, MA
Gu-Yeon Wei, Harvard University, Cambridge, MA
COEXE: An Efficient Co-Execution Architecture for Real-Time Neural Network Services
FLOPS: Efficient On-Chip Learning for Optical Neural Networks Through Stochastic Zeroth-Order Optimization
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs
A Two-Way SRAM Array Based Accelerator for Deep Neural Network On-Chip Training
Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference
Jason M. Fung
Jeronimo Castrillon
Jian-Jia Chen
Noel Menezes
Partha Pande
Preeti R. Panda
Rajiv Joshi
Seda Ogrenci Memik
Vijay Raghunathan
Yu Cao
Easy Deadlock Verification and Debug with Advanced Formal Verification
Laurent Arditi - Arm, Ltd., Valbonne, France
Vincent Abikhattar - Arm, Ltd., Sophia-Antipolis, France
Joe Hupcey III - Mentor, A Siemens Business, Fremont, CA
Jeremy Levitt - Mentor, A Siemens Business, Fremont, CA
Achieve Better Communication in Your UVM TB Using These Obscure UVM Classes
Pavan Yeluri - NVIDIA Corp., Hyderabad, India
Ranjith Nair - NVIDIA Corp., Hyderabad, India
A CPU Power Distribution Network Optimization Method Considering Routing Congestion with Genetic Algorithm
Huajun Wen - MediaTek, Inc., Austin, TX
Hsinchen Chen - MediaTek, Inc., Austin, TX
Wei Chang - Univ. of Southern California, Los Angeles, CA
Thomas Drablos - MediaTek, Inc., Austin, TX
Weighted Partial Gating Selection Algorithm for Power Reduction in Scan Based Tests
Kavithaa Rajagopalan - Texas Instruments India Pvt. Ltd., Bangalore, India
WIlson Pradeep - Texas Instruments India Pvt. Ltd., Bangalore, India
Shreya Gupta - Malaviya National Institute of Technology & Texas Instruments India Pvt. Ltd., Jaipur, India
PCI Gen4 Channel Optimization Using Machine Learning
Wook Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Raewoon You - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Jun So Park - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
The Path Towards Battery-Free and Forever-Battery Life for Internet of Things
Masoud Zargari - Atmosic Technologies, Campbell, CA
58th DAC
DAC 58 is July 11-15, 2021 in San Francisco
DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP).
