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Late Breaking Results Submissions

Prospective authors are invited to submit a late breaking results (LBR) paper (2 pages, two-column format) describing original work. LBR papers should cover new research in any area relevant to the normal paper submission for DAC. Sufficient work must have been completed to indicate viability of the work, but by their nature LBR papers typically outline new and exciting results. Papers must use the template provided on the DAC web site. Accepted LBR submissions will be presented at a poster session where the LBR poster presenters will showcase their work and get timely feedback from professionals including academia, EDA industries, designers, and makers. At least one author must be present at the poster session. Publication in IEEE Xplore is contingent on registration for the conference and presentation at the poster session.

Once a LBR paper is accepted, authors are stongly reccommeded to create a 1-minute video articulating the key ideas and innovations. The video should be a publicly accessible link to introduce the work to the conference audience. There is no restriction on the creativity or content of the video. Examples of video can be slides with narration, video of a prototype, and simulation system demo.

SUBMISSION FORMAT

Prospective authors are invited to submit a LBR paper (2 pages, two-column format) describing original work. Submissions that are accepted to the LBR program are required to have one author register to the conference and present a poster in the DAC LBR session. LBR does not encourage resubmission of papers rejected at other venues. If a paper is submitted to LBR, after an earlier version has been rejected, the authors should disclose major innovations or breakthroughs to earlier submissions. No duplicate or concurrent submissions are allowed.

Manuscript Submission

A title, abstract (approximately 100 words), a list of all co-authors and the entire Late breaking work must be submitted by March 5, 2020

Each submitted manuscript must discuss original work that has not been previously published in other indexed research databases. Authors are responsible for ensuring that their manuscript meets the submission guidelines outlined in the tabs at the top of this page. There will be no opportunity for re-submission to correct any issues. Your manuscript will be reviewed as a finalized manuscript. Preliminary submissions will be at a disadvantage.

SUBMISSION TIMELINE

Submission Opens - January 27, 2020, 5:00PM (MST), (-7:00 GMT)
Manuscript Deadline - March 5, 2020, 4:00PM (MST), (-8:00 GMT)
Notification of Acceptance - April 2, 2020
Confirmation Forms - April 6, 2020, 5:00PM (MST), (-7:00 GMT)
Copyright Forms Due - April 9, 2020, 5:00PM (MST), (-7:00 GMT)
Final Papers Due - April 9, 2020, 5:00PM (MST), (-7:00 GMT)

Submission Rules

Submitter must enter names, affiliations, city, state, country and email address of ALL co-authors. The addition of new co-authors will not be permitted after March 5, 2020.
DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)’ own previous work or affiliations in the bibliographic citations being in the third person. Avoid the use of “omitted for blind review” in the bibliography section.
The manuscript must be within 2 pages, double-columned, 9 or 10-pt font, in PDF format only, and be a readable file.
Title should start with “Late Breaking Results: ...”
The manuscript should focus on the contributions in these two pages and limit background and related work to the most essential.
An author of each accepted LBR submission is required to:
- Bring a poster following the instructions provided.
- Sign and submit a Rights and Release form.
In addition:
- One co-author on the presentation is required to pay the $ Speaker Registration Fee.
- The speaker must present the poster at the conference.

Copyright Information

All LBR presentations that are accepted to DAC will be required by IEEE to sign a Rights and Release form. Please note that paper copyright forms are no longer accepted and IEEE does not accept any addendum to their forms.

The Rights and Release form will be sent to accepted authors electronically, and authors will be required to complete an electronic version of one of three available form options through the IEEE submission system in order to participate in the conference.

IEEE's Publishing Policy can be found here and the Author Rights page can be found here.

Any issues/questions authors have regarding the copyright form or IEEE Policy can be addressed here.

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Submission Categories

Authors of LBR poster submissions are required to specify a category from the list below. Authors of submissions that cover cross-cutting topics (e.g. low-power, multi-core architecture, 3-D, emerging technologies, IoT, etc.) should select a category that is closest to the essential contribution of the submission. Your selection should be based on the consideration of which expertise group of people would better review your submissions.

AUTONOMOUS SYSTEMS

AS1. Autonomous Systems (Automotive, Robotics, Drones)

AS1.1 Autonomous Systems Design Tools and Methodologies
AS1.2 Autonomous Systems Architectures
AS1.3 Autonomous Systems Safety and Reliability

DESIGN

DES1. Design of Cyber-physical Systems and IoT

DES1.1 Cyber-physical systems and Internet-of-Things (IoT) platforms
DES1.2 Low-power and energy-efficient design techniques for IoT
DES1.3 Partitioned Edge/hub/cloud processing
DES1.4 Dependable and safety-critical embedded system design
DES1.5 Networking and storage system design
DES1.6 Advanced wireless communication system design
DES1.7 Machine Learning for Cyber-Physical Systems

DES2. SoC, Heterogeneous, and Reconfigurable Architectures

DES2.1 Architectures for stochastic, statistical and approximate computing
DES2.2 SoC and heterogeneous multi- and many-core architectures
DES2.3 Run-time and design-time reconfigurable processor architectures

DES3. Approximate Computing for AI/ML

DES3.1 Quantization, Pruning and Model Compression
DES3.2 Approximate and Stochastic hardware for AI/ML
DES3.3 Cross-layer approximations and accuracy tradeoffs in AI/ML

DES4. AI/ML System Design

DES4.1 HW and system architectures for neural network training and inference
DES4.2 Architectures for emerging AI/ML algorithms (beyond neural networks)
DES4.3 AI/ML Architectures with Beyond-CMOS technologies
DES4.4 Software frameworks and libraries for AI/ML
DES4.5 Automating AI/ML system design (AutoML)

DES5. Emerging Models of Computation

DES5.1 Biologically-based or biologically-inspired computing systems
DES5.2 Design automation for system & synthetic biology
DES5.3 Neuromorphic and brain-inspired computing
DES5.4 Quantum computing

DES6. Digital and Analog Circuits

DES6.1 2.5-D and 3-D integrated circuit designs
DES6.2 Clock network and interconnect designs
DES6.3 Low-power and energy-efficient digital circuits
DES6.4 Analog, mixed-signal and RF circuits
DES6.5 Circuits for advanced wireless communication
DES6.6 Memory design

DES7. Emerging Device Technologies

DES7.1 New transistor structures, beyond-CMOS devices (e.g., steep-slope devices, spintronics), and new process technologies
DES7.2 Nanotechnologies, nanowires, nanotubes
DES7.3 Emerging non-volatile memory devices
DES7.4. New Architectures with Emerging Technologies

EDA

EDA1. System-on-Chip Design Methodology

EDA1.1 System-on-Chip (SoC) specification, modeling, analysis, simulation, and verification
EDA1.2 Application-specific processor design tools
EDA1.3 Design tools for accelerator-rich architectures and heterogeneous multi-cores
EDA1.4 Tools for reconfigurable computing
EDA1.5 HW/SW co-design, interface synthesis, and co-verification
EDA1.6 System-level methods for reliability and aging

EDA2. In-Package and On-Chip Communication and Networks-on-Chip

EDA2.1 Communication architecture modeling and analysis
EDA2.2 Synthesis and optimization of communication architectures
EDA2.3 NoC architectures and design methodologies
EDA2.4 Communication architectures using alternative technologies (e.g., nanophotonics, RF, 3D, etc.)

EDA3. Cross-Layer Power Analysis and Low-Power Design

EDA3.1 System-level low-power design analysis and management
EDA3.2 Architectural power reduction techniques and analysis tools
EDA3.3 Low-power circuit design methods and tools
EDA3.3 Low-power circuit design methods and tools
EDA3.4 System-level and architectural thermal analysis and management

EDA4. RTL/Logic Level and High-level Synthesis

EDA4.1 Combinational, sequential and asynchronous logic synthesis
EDA4.2 Technology mapping, cell-based design and optimization
EDA4.3 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods
EDA4.4 Synthesis for FPGAs
EDA4.5 Synthesis for circuits in emerging device technologies
EDA4.6 Machine Learning techniques for synthesis

EDA5. Analog Design, Simulation, Verification and Test

EDA5.1 Analog, mixed-signal, and RF design methodologies
EDA5.2 Automated synthesis and optimization of analog designs
EDA5.3 Analog, mixed-signal, RF, electromagnetic, substrate noise modeling and simulation
EDA5.4 Model order reduction techniques for analog/RF designs

EDA6. Digital Design, Timing and Simulation

EDA6.1 Timing analysis and simulation/delay modeling
EDA6.2 Power/signal integrity analysis and simulation
EDA6.3 Process technology modeling
EDA6.4 Circuit- and gate-level power/thermal analysis

EDA7. Physical Design and Verification, Lithography and DFM

EDA7.1 Floorplanning, partitioning, placement
EDA7.2 Interconnect and clock network planning and synthesis
EDA7.3 Cross-layer placement and routing optimization for timing/power/yield
EDA7.4 Post-Layout and post-silicon optimizations
EDA7.5 Physical design of 3-D integrated circuits
EDA7.6 Reticle enhancement, lithography-related design optimizations and design rule checking
EDA7.7 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
EDA7.8 Machine Learning Techniques for Physical Design

EDA8. Design Verification and Validation

EDA8.1 Functional and transaction-level modeling and validation, coverage and test generation for hardware and embedded systems
EDA8.2 Emulation and hardware acceleration
EDA8.3 Formal and semi-formal verification and verification technologies
EDA8.4 Verification of firmware, software, and hybrid hardware/software systems
EDA8.5 Machine learning techniques for verification
EDA8.6 Post-silicon design validation and debug

EDA9. Manufacturing Test and Reliability

EDA9.1 Fault modeling, ATPG, DFT, BIST, compression
EDA9.2 Memory, FPGA and emerging technology test and reliability
EDA9.3 SoC, board- and system-level test
EDA9.4 Post-silicon test and defect diagnosis
EDA9.5 Analog/mixed-signal/RF verification and test
EDA9.6 Noise, aging induced delays, and reliability analysis

ESS

ESS1. Embedded Software

ESS1.1 Embedded software verification methodologies
ESS1.2 Embedded operating systems, middleware, runtime support, resource management, and virtual machines
ESS1.3 Software techniques for multicores, GPUs, and multithreaded embedded architectures
ESS1.4 Compilation strategies, code transformation and parallelization techniques for embedded systems
ESS1.5 Domain-specific embedded libraries (e.g., for machine learning)
ESS1.6 Embedded Software Development Case Studies (e.g., ANDROID development, ARM-based systems, etc.)
ESS1.7 Operating Systems and Middleware
ESS1.8 Software Design and Analysis

ESS2. Embedded System Design Methodologies

ESS2.1 Embedded system specification, virtual prototyping and simulation
ESS2.2 Embedded system synthesis and optimization
ESS2.3 Analysis of embedded system QoS metrics - performance, battery life, reliability, etc.
ESS2.4 Design methodologies for self-aware, self-adaptive and autonomous embedded systems
ESS2.5 Design methodology for mobile, wearable and Internet of Things devices
ESS2.6 Machine Learning for Embedded Design Methoidologies

ESS3. Embedded Storage and I/O Systems

ESS3.1 On-chip memory architectures and management: Scratchpads, compiler controlled memories, etc.
ESS3.2 Embedded storage systems organization and management
ESS3.3 Memory and Storage hierarchies with emerging memory technologies
ESS3.3 Memory and Storage hierarchies with emerging memory technologies

ESS4. Near-Memory and In-Memory Computing

ESS4.1 Memory architecture and management for emerging memory technologies
ESS4.2 Data reorgainzation engines

ESS5 Time-Critical System Design

ESS5.1 Real-time analysis and tool flows
ESS5.2 WCET methods and tools for embedded hardware/software systems
ESS5.3 Mixed-Criticality system design
ESS5.4 HW-SW integration and system-level design for timing-critical systems
ESS5.5 Timing predictable resource sharing and management

SECURITY/PRIVACY

SEC1. Hardware Security I: Primitives, Architectures, Design, and Test

SEC1.1 Hardware security primitives for cryptography, key generation, and authentication
SEC1.2 Trusted IP and system-on-chip (SoC) design and manufacturingSEC1.3 Trusted IP and system-on-chip (SoC) design and manufacturing
SEC1.3 Emerging technologies (Nanoscale devices, 3D, etc.) and security
SEC1.4 Hardware security verification, validation and test

SEC2. Embedded and Cross-Layer Security

SEC2.1 Embedded software and system-level techniques for security
SEC2.2 Architectural support for software and embedded systems security
SEC2.3 Cyber-physical systems and IoT security
SEC2.4 Embedded security: metrics, models, verification and validation
SEC2.5 Machine learning for cyber defense
SEC2.6 Security vulnerabilities in artificial intelligence

SEC2. Embedded and Cross-Layer Security

SEC3.1 Embedded software and system-level techniques for security
SEC3.2 Architectural support for software and embedded systems security
SEC3.3 Cyber-physical systems and IoT security
SEC3.4 Embedded security: metrics, models, verification and validation
SEC3.5 Machine learning for cyber defense
SEC3.6 Security vulnerabilities in artificial intelligence

REVIEW AND SELECTION PROCESS

The papers are peer-reviewed and will be published as is (except for the addition of author names, affiliations, and acknowledgements) after acceptance. NO OTHER CHANGES ARE ALLOWED.
DAC will still ensure that there are no conflicts of interest between authors and reviewers.

The reported result should be novel and interesting enough to warrant an acceptance as late breaking.
Additional criteria will include:

Importance of the problem and quality of the technical contribution (design, method, research) described in the manuscript.
Originality of the concepts used and described (whether tools, methods or design). Advances over previous approaches should be reflected by describing the significant improvement in the results section. Comparisons with other approaches are also important to justify the advancement claimed in your manuscript.
Significance of the results obtained or expected with clues - by measurable quantitative criteria (runtime for tools, optimal results, time for design process steps, simplification or automation of manual effort, etc.).
Degree of experimental validation of the concepts. Use in real designs or widely accepted benchmarks with measurable criteria for results is highly desirable, if not essential.
A good discussion of limitations of the approach and concepts, and possible areas for future improvement.
The quality of manuscript writing, use of English, organization and clarity of presentation.

Conflict of Interest

To further strengthen the review process, each submitter is asked to identify any Technical Program Committee (TPC) members with whom s/he has conflict of interests (COI). The TPC list is available below.

An author has a conflict with a member of the Technical Program Committee if one or more of the situations below holds:

Advisor-advisee relation
Co-authors of a paper (published and/or under review) in the last 24 months
Author and TPC member are from the same institution
Co-PIs of a grant in the last 2 years
Close personal or family relationship

The submitter should indicate the COIs of all authors with members of the Technical Program Committee by November 26, 2019. Failure to do so may lead to automatic rejection of the submission.

SUBMISSIONS ARE NOW CLOSED

Submission Deadline

March 5, 2020, 4:00PM (MST), (-8:00 GMT)

CHAIR Information

Vijaykrishnan Narayanan
Late Breaking Results Chair
Email

Submission Site Questions

Vijaykrishnan Narayanan
Late Breaking Results Chair
Email