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Late Breaking Results Submissions

Prospective authors are invited to submit a late breaking results (LBR) paper (2 pages, two-column format) describing original work. LBR papers should cover new research in any area relevant to the normal paper submission for DAC. Sufficient work must have been completed to indicate viability of the work, but by their nature LBR papers typically outline new and exciting results. Papers must use the template provided on the DAC web site. Accepted LBR submissions will be presented at a poster session where the LBR poster presenters will showcase their work and get timely feedback from professionals including academia, EDA industries, designers, and makers. At least one author must be present at the poster session. Publication in IEEE Xplore is contingent on registration for the conference and presentation at the poster session.

Once a LBR paper is accepted, authors are strongly recommended to create a 1-minute video articulating the key ideas and innovations. The video should be a publicly accessible link to introduce the work to the conference audience. There is no restriction on the creativity or content of the video. Examples of video can be slides with narration, video of a prototype, and simulation system demo.

SUBMISSION FORMAT

Prospective authors are invited to submit a LBR paper (2 pages, two-column format) describing original work. Submissions that are accepted to the LBR program are required to have one author register to the conference and present a poster in the DAC LBR session. LBR does not encourage resubmission of papers rejected at other venues. If a paper is submitted to LBR, after an earlier version has been rejected, the authors should disclose major innovations or breakthroughs to earlier submissions. No duplicate or concurrent submissions are allowed.

Manuscript Submission

A title, abstract (approximately 100 words), a list of all co-authors and the entire Late breaking work must be submitted by March 5, 2021.

Each submitted manuscript must discuss original work that has not been previously published in other indexed research databases. Authors are responsible for ensuring that their manuscript meets the submission guidelines outlined in the tabs at the top of this page. There will be no opportunity for re-submission to correct any issues. Your manuscript will be reviewed as a finalized manuscript. Preliminary submissions will be at a disadvantage.

SUBMISSION TIMELINE

Submission Opens - January 29, 2021, 5:00PM (PST)

Manuscript Deadline - March 5, 2021, 4:00PM (PST)

Notification of Acceptance - April 2, 2021

Confirmation Forms - April 6, 2021, 5:00PM (PDT)

Copyright Forms Due - April 9, 2021, 5:00PM (PDT)

Final Papers Due - April 9, 2021, 5:00PM (PDT)

Submission Rules

Submitter must enter names, affiliations, city, state, country and email address of ALL co-authors. The addition of new co-authors will not be permitted after March 5, 2021.
DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)’ own previous work or affiliations in the bibliographic citations being in the third person. Avoid the use of “omitted for blind review” in the bibliography section.
The manuscript must be within 2 pages, double-columned, 9 or 10-pt font, in PDF format only, and be a readable file.
Title should start with “Late Breaking Results: ...”
The manuscript should focus on the contributions in these two pages and limit background and related work to the most essential.
An author of each accepted LBR submission is required to:
Bring a poster following the instructions provided.
Sign and submit a Rights and Release form.
In addition:
One co-author on the presentation is required to pay the $ Speaker Registration Fee.
The speaker must present the poster at the conference.

DUPLICATE SUBMISSIONS

DAC adheres to strict rules regarding duplicate submissions. Submissions must be clearly novel and distinct with respect to other submissions to DAC 2021, concurrent submissions to other conferences and previously published work.

All closely related work should be properly referenced. If such related work is authored by one of the co-author(s) of the manuscript in submission, it should be referenced as if it were written by others.
Any extended version of the submitted manuscript should not be submitted or under review before the formal notification of the DAC ‘s review decision.
If any co-author has any paper that may be perceived as having overlapping contributions and that is simultaneously under review by another venue, such papers must be disclosed in the submission process.

Submissions which fail to follow the above guidelines will be automatically rejected. In serious cases, the authors’ names will be reported to IEEE and kept in records, as well as sent to the Technical Chair or the Editor of the venue where the duplicate manuscript was submitted; the authors may be banned from publishing at future DAC conferences.

DISCLOSURE PROCESS FOR UNPUBLISHED WORK

When submitting to DAC, authors face a dilemma. DAC has a blind review process in which the author’s identity remains anonymous. However, the submission rules compel the authors to cite relevant publications that have already been accepted or are under review by another conference (such as ICCAD, DATE, ASP-DAC, etc.). Disclosing these papers under the citation list reveals the authors’ identities. To circumvent this issue, DAC has implemented a disclosure process.

When submitting a paper, the authors are asked to list each relevant paper that has not yet been published and include the corresponding pdf of the paper. The LBR Chair will be able to check for self-plagiarism and relevance without revealing the author identities to the reviewers. Failure to disclose such papers will be considered as omission of closely related work and subject to the same penalties outlined in the Duplicate Submissions, as discussed in the section.

FREQUENTLY ASKED QUESTIONS

How should I submit the conflict of interest (COI) information?

Submitters should report COIs of all co-authors with respect to members of the Technical Program Committee upon submission. However, it is recommended that submitters work on marking COIs as soon as they submit their manuscript's abstract, since this task may require some time, which is often scarce in the final sprint towards the completion of a manuscript's submission. Modifications to marked COIs can be made any time prior to the manuscript deadline.

Authors are asked to mark all the TPC members who have COIs with at least one of the authors at the time of abstract registration. Do not mark any members of the Technical Program Committee as COI where there is in fact COI.

What if authors failed to identify TPC members with COI?

DAC assumes that authors have no additional COIs with TPC members, beside those that have been declared at the time of manuscript submission. If a manuscript is found to have failed in identifying a COI, during or after the paper selection process, the submitted manuscript will be automatically rejected. Same hold if members of the Technical Program Committee are marked as COI where there is in fact no COI.

What is the DAC LBR manuscript timeline?

DAC will follow the timeline below in processing, selecting and publishing research manuscripts:

Submission Opens - January 29, 2021, 5:00PM (PST)

Manuscript Deadline - March 5, 2021, 4:00PM (PST)

Notification of Acceptance - April 2, 2021

Confirmation Forms - April 6, 2021, 5:00PM (PDT)

Copyright Forms Due - April 9, 2021, 5:00PM (PDT)

Final Papers Due - April 9, 2021, 5:00PM (PDT)

Which category should I select when I submit my manuscript?

The Call for Contributions lists several categories; please select the most appropriate primary topic when submitting your abstract. Authors of submissions that cover cross-cutting topics should select a category that is closest to the essential contribution of the submission. Submissions will be asked to select a broad category (ex. “EDA1. System-on-chip and HW/SW Codesign. A complete list of available categories and topic areas can be found in the CFP. Please note that their separate categories for electronic design automation topics, embedded systems and software topics, autonomous electronic design, design and system security, and electronic design topics.

How do I avoid referencing my own work to ensure the integrity of the blind review process?

To satisfy the criteria for a blind review process, the Call for Contributions states that any references to the author(s) own previous work or affiliations in the bibliographic citations must be in the third person. For the blind review process, DO NOT LIST THE NAMES OR AFFILIATIONS OF ANY OF THE AUTHORS ANYWHERE ON THE MANUSCRIPT, except in the references section (if citation to prior work is required).

Example: A. and B. presented a method for listing self-referential citations in [5]. 

[5] A. A and B. B, How to write a research DAC paper, 2020.

DO NOT use “omitted for blind review” to cite authors’ own papers. Describe all related papers published by you as if they were written by others.

Citation of authors’ unpublished papers is not allowed, including citation of potential double and/or simultaneous submissions. If this situation arises, submitters must follow the disclosure requirements to disclose their (or thier co-authors) related work that is under review or accepted for publication.

Copyright Information

One author of each accepted paper that is submitted to DAC for publication in the official conference proceedings is required by IEEE to sign a copyright form. Please note that paper copyright forms are no longer accepted and IEEE does not accept any addendum to their forms.

Copyright forms can be found here. These copyright samples are for your information only. Authors will be required to complete an electronic version of one of these forms through the IEEE submission system if their paper is accepted.
IEEE’s Publishing Policy can be found here and the Author Rights page can be found here.
Any issues/questions authors have regarding the copyright form or IEEE Policy may be addressed to IEEE.

Submission Categories

Authors of research manuscripts are required to specify main category from the list below. Authors of submissions that cover cross-cutting topics should select a category that is closest to the essential contribution of the submission. Your selection should take into consideration the likely expertise of the group of people who will serve in reviewing manuscripts for each category.

AUTONOMOUS SYSTEMS

AS1. Autonomous Systems (Automotive, Robotics, Drones)

AS1.1 Autonomous Systems Design Tools and Methodologies
AS1.2 Autonomous Systems Architectures
AS1.3 Autonomous Systems Safety and Reliability

DESIGN

DES1. Design of Cyber-physical Systems and IoT

DES1.1 Cyber-physical systems and Internet-of-Things (IoT) platforms
DES1.2 Low-power and energy-efficient design techniques for IoT
DES1.3 Partitioned Edge/hub/cloud processing
DES1.4 Dependable and safety-critical embedded system design
DES1.5 Networking and storage system design
DES1.6 Advanced wireless communication system design

DES2. SoC, Heterogeneous, and Reconfigurable Architectures

DES2.1 Architectures for stochastic, statistical and approximate computing
DES2.2 SoC and heterogeneous multi- and many-core architectures
DES2.3 Run-time and design-time reconfigurable processor architectures
DES2.4: 2.5D/3D heterogeneous integration of compute, memory and communication platforms

DES3. Approximate Computing for AI/ML

DES3.1 Approximation techniques for neural network training and inference
DES3.2 Application-driven approximations in hardware architecture and design for AI/ML
DES3.3 AI/ML architecture-algorithm co-design for approximate computing

DES4. AI/ML System Design

DES4.1 Hardware and architecture of AI/ML systems
DES4.2 Software and algorithms for AI/ML
DES4.3 System level co-design and co-optimizations for AI/ML

DES5. Emerging Models of Computation

DES5.1 Biologically-based or biologically-inspired computing systems
DES5.2 Design automation for system & synthetic biology
DES5.3 Neuromorphic and brain-inspired computing

DES6. Digital and Analog Circuits

DES6.1 2.5-D and 3-D integrated circuit designs
DES6.2 Clock network and interconnect designs
DES6.3 Low-power and energy-efficient digital circuits
DES6.4 Analog, mixed-signal and RF circuits
DES6.5 Circuits for advanced wireless communication
DES6.6 Memory design

DES7. Emerging Device Technologies

DES7.1 New transistor structures, beyond-CMOS devices (e.g., steep-slope devices, spintronics), and new process technologies
DES7.2 Nanotechnologies, nanowires, nanotubes
DES7.3 Emerging non-volatile memory devices

DES8. Quantum Computing

DES8.1 Quantum computing applications and algorithms
DES8.2 Quantum computing hardware architecture and design
DES8.3 Quantum computing technology

EDA

EDA1. System-on-Chip Design Methodology

EDA1.1 System-on-Chip (SoC) specification, modeling, analysis, simulation, and verification
EDA1.2 Application-specific processor design tools
EDA1.3 Design tools for accelerator-rich architectures and heterogeneous multi-cores
EDA1.4 Tools for reconfigurable computing
EDA1.5 HW/SW co-design, interface synthesis, and co-verification
EDA1.6 System-level methods for reliability and aging

EDA2. In-Package and On-Chip Communication and Networks-on-Chip

EDA2.1 Communication architecture modeling and analysis
EDA2.2 Synthesis and optimization of communication architectures
EDA2.3 NoC architectures and design methodologies
EDA2.4 Communication architectures using alternative technologies (e.g., nanophotonics, RF, 3D, etc.)

EDA3. Cross-Layer Power Analysis and Low-Power Design

EDA3.1 System-level low-power design analysis and management
EDA3.2 Architectural power reduction techniques and analysis tools
EDA3.3 Low-power circuit design methods and tools
EDA3.4 System-level and architectural thermal analysis and management

EDA4. RTL/Logic Level and High-level Synthesis

EDA4.1 Combinational, sequential and asynchronous logic synthesis
EDA4.2 Technology mapping, cell-based design and optimization
EDA4.3 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods
EDA4.4 Synthesis for FPGAs
EDA4.5 Synthesis for circuits in emerging device technologies

EDA5. Analog Design, Simulation, Verification and Test

EDA5.1 Analog, mixed-signal, and RF design methodologies
EDA5.2 Automated synthesis and optimization of analog designs
EDA5.3 Analog, mixed-signal, RF, electromagnetic, substrate noise modeling and simulation
EDA5.4 Model order reduction techniques for analog/RF designs

EDA6. Digital Design, Timing and Simulation

EDA6.1 Timing analysis and simulation/delay modeling
EDA6.2 Power/signal integrity analysis and simulation
EDA6.3 Process technology modeling
EDA6.4 Circuit- and gate-level power/thermal analysis

EDA7. Physical Design and Verification, Lithography and DFM

EDA7.1 Floorplanning, partitioning, placement
EDA7.2 Interconnect and clock network planning and synthesis
EDA7.3 Cross-layer placement and routing optimization for timing/power/yield
EDA7.4 Post-Layout and post-silicon optimizations
EDA7.5 Physical design of 3-D integrated circuits
EDA7.6 Reticle enhancement, lithography-related design optimizations and design rule checking
EDA7.7 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
EDA7.8 Device-, circuit- and gate-level techniques for reliability (e.g.: manufacturing variations, aging, etc.)

EDA8. Design Verification and Validation

EDA8.1 Functional and transaction-level modeling and validation, coverage and test generation for hardware and embedded systems
EDA 8.2 Emulation and hardware acceleration
EDA8.3 Formal and semi-formal verification and verification technologies
EDA8.4 Verification of firmware, software, and hybrid hardware/software systems
EDA8.5 Machine learning techniques for verification
EDA8.6 Post-silicon design validation and debug
EDA8.7 Validation of cognitive systems

EDA9. Manufacturing Test and Reliability

EDA9.1 Fault modeling, ATPG, DFT, BIST, compression
EDA9.2 Memory, FPGA and emerging technology test and reliability
EDA9.3 SoC, board- and system-level test
EDA9.4 Post-silicon test and defect diagnosis
EDA9.5 Analog/mixed-signal/RF verification and test
EDA9.6 Noise, aging induced delays, and reliability analysis

ESS

ESS1. Embedded Software

ESS1.1 Embedded software verification methodologies
ESS1.2 Embedded operating systems, middleware, runtime support, resource management, and virtual machines
ESS1.3 Software techniques for multicores, GPUs, and multithreaded embedded architectures
ESS1.4 Compilation strategies, code transformation and parallelization techniques for embedded systems
ESS1.5 Domain-specific embedded libraries (e.g., for machine learning)
ESS1.6 Embedded Software Development Case Studies (e.g., ANDROID development, ARM-based systems, RISC-V based systems etc.)

ESS2. Embedded System Design Methodologies

ESS2.1 Embedded system specification, virtual prototyping and simulation
ESS2.2 Embedded system synthesis and optimization
ESS2.3 Analysis of embedded system QoS metrics - performance, battery life, reliability, etc.
ESS2.4 Design methodologies for self-aware, self-adaptive and autonomous embedded systems
ESS2.5 Design methodology for mobile, wearable and Internet of Things devices

ESS3. Embedded Memory, Storage and Networking

ESS3.1 On-chip memory architectures and management: Scratchpads, compiler controlled memories, etc.
ESS3.2 Embedded storage systems organization and management
ESS3.3 Memory and Storage hierarchies with emerging memory technologies

ESS4. Near-Memory and In-Memory Computing

ESS4.1 Memory architecture and management for emerging memory technologies
ESS4.2 Data reorganization engines
ESS4.3: In-memory and near-memory computing for AI/ML including neural networks

ESS5 Time-Critical System Design

ESS5.1 Real-time analysis and tool flows
ESS5.2 WCET methods and tools for embedded hardware/software systems
ESS5.3 Mixed-Criticality system design

SECURITY/PRIVACY

SEC1. Hardware Security: Primitives, Architecture, Design & Test

SEC1.1 Hardware security primitives for cryptography, key generation, and authentication
SEC1.2 Trusted IP and system-on-chip (SoC) design and manufacturing
SEC1.3 Emerging technologies (Nanoscale devices, 3D, etc.) and security
SEC1.4 Hardware security verification, validation and test
SEC1.5 Post-quantum crypto algorithms and implementations

SEC2. Hardware Security: Attack and Defense

SEC2.1 Hardware-enabled side-channel attacks and defenses
SEC2.2 Software-driven side-channel attacks and defenses
SEC2.3 AI/ML-based attacks and defenses
SEC2.4 Adversarial machine learning attacks and defenses
SEC2.5 Hardware supply chain protection and anti-counterfeiting
SEC2.6 Reverse engineering and hardware obfuscation

SEC3. Embedded and Cross-Layer Security

SEC3.1 Embedded software and system-level techniques for security
SEC3.2 Architectural support for software and embedded systems security
SEC3.3 Cyber-physical systems and IoT security
SEC3.4 Embedded security: metrics, models, verification and validation
SEC3.5 Machine learning for cyber defense

REVIEW AND SELECTION PROCESS

The papers are peer-reviewed and will be published as is (except for the addition of author names, affiliations, and acknowledgements) after acceptance. NO OTHER CHANGES ARE ALLOWED.
DAC will still ensure that there are no conflicts of interest between authors and reviewers.

The reported result should be novel and interesting enough to warrant an acceptance as late breaking.
Additional criteria will include:

Importance of the problem and quality of the technical contribution (design, method, research) described in the manuscript.
Originality of the concepts used and described (whether tools, methods or design). Advances over previous approaches should be reflected by describing the significant improvement in the results section. Comparisons with other approaches are also important to justify the advancement claimed in your manuscript.
Significance of the results obtained or expected with clues - by measurable quantitative criteria (runtime for tools, optimal results, time for design process steps, simplification or automation of manual effort, etc.).
Degree of experimental validation of the concepts. Use in real designs or widely accepted benchmarks with measurable criteria for results is highly desirable, if not essential.
A good discussion of limitations of the approach and concepts, and possible areas for future improvement.
The quality of manuscript writing, use of English, organization and clarity of presentation.

Conflict of Interest

To further strengthen the review process, each submitter is asked to identify any Technical Program Committee (TPC) members with whom s/he has conflict of interests (COI). The TPC list is available below.

An author has a conflict with a member of the Technical Program Committee if one or more of the situations below holds:

Advisor-advisee relation
Co-authors of a paper (published and/or under review) in the last 24 months
Author and TPC member are from the same institution
Co-PIs of a grant in the last 2 years
Close personal or family relationship

The submitter should indicate the COIs of all authors with members of the Technical Program Committee upon submission. Failure to do so may lead to automatic rejection of the submission. If the submitter marks members of the Technical Program Committee as COI where there is in fact no COI, which may also lead to automatic rejection.

Submission Deadline

March 5, 2021, 5:00PM (PST), (-8:00 GMT)

CHAIR Information

John Sampson
Portland State University
Email

Submission Site Questions

Alexis Bauer Kolak
Education Director
Email