Dr. H. -S. Philip Wong
Future electronic systems will continue to rely on, and increasingly benefit from, the advances in semiconductor technology as they have had for more than five decades. Since its inception, the semiconductor industry has used a physical dimension (minimum gate length of a transistor) as a means to gauge continuous technology advancement. This metric is all but obsolete today. Density is what drives the benefits of new device technologies for computation – the primary application driver for semiconductors. Going forward, we will use a three-prong metric that consists of logic density (DL), memory bit density (DM), and interconnect density between logic and memory (DC) as a means to capture how advances in semiconductor device technologies enable system level benefits. Because DL and DM will increase at a slower rate than the historical trends, technologies that address the connectivity will become primary drivers for technology advancement. This trend is already visible in HPC products that progressively leverage more capable packaging technologies including 3D chip stacking. Indeed, vertical interconnect density associated with advanced packaging featured about three orders of magnitude improvement in the last decade alone. Scaling vertical interconnect pitch to sub-100 nm would enable another four orders of magnitude improvement. As such, there is plenty of room for system-level advances based on 3D ICs. The distinction between on-die connectivity (vias and on-chip interconnect wires) and off-chip connectivity (e.g. TSVs and micro-bumps) will become increasingly blurred. Wafer-level monolithic integration technologies and packaging technologies will smoothly blend into one another. New design tools that optimally perform system partitioning will become indispensable.
Biography: H.-S. Philip Wong is the Willard R. and Inez Kerr Bell Professor in the School of Engineering at Stanford University. In 2018, he was on leave from Stanford and was the Vice President of Corporate Research at TSMC, the largest semiconductor foundry in the world. Since 2020, he has been the Chief Scientist of TSMC. He joined Stanford University as Professor of Electrical Engineering in September, 2004. From 1988 to 2004, he was with the IBM T.J. Watson Research Center. He is a Fellow of the IEEE and received the IEEE Electron Devices Society J.J. Ebers Award. He served as the Editor-in-Chief of the IEEE Transactions on Nanotechnology (2005 – 2006), sub-committee Chair of the ISSCC (2003 – 2004), General Chair of the IEDM (2007), and is currently the Chair of the IEEE Executive Committee of the Symposia of VLSI Technology and Circuits. He received the honorary doctorate degree from Institut Polytechnique de Grenoble, France. Professor Wong and his students have won best paper awards at premier conferences such as the International Solid-State Circuits Conference (ISSCC) and Symposia on VLSI. He is the faculty director of the Stanford Non-Volatile Memory Technology Research Initiative (NMTRI), and is the founding Faculty Co-Director of the Stanford SystemX Alliance – an industrial affiliate program focused on building systems.