Speedcore Validation Chip Passes Rigorous Testing Suite and Verified as Fully Functional
Complex Designs Run at 500MHz Across All Operating Conditions
Santa Clara, Calif., January 17, 2018 – Achronix Semiconductor Corporation, a leader in FPGA-based hardware accelerator devices and embedded FPGA (eFPGA) intellectual property (IP), announced today that it completed full silicon verification of its Speedcore™ eFPGA production validation chip built on TSMC 16nm FinFET+ process technology. Rigorous bench and ATE tests were completed across full operating conditions to verify the complete functionality of the Speedcore test chip.
Speedcore IP is a fully permutable architecture technology that can be built with densities ranging from less than 10,000 look-up-tables (LUTs) up to...
Cross-Licensing Agreement Brings Next-Level Wafer-Level Noise Characterization, Enabling High Throughput Measurements with Advanced Probing Technologies
SAN JOSE, CALIF. –– December 12, 2017 –– ProPlus Design Solutions Inc. and MPI Corporation today announced a strategic partnership agreement and immediate availability of a characterization and modeling solution that integrates ProPlus’ SPICE modeling and noise characterization solution with MPI’s advanced probing technologies.
The integrated solution offers seamless support of the MPI probe stations to perform automated measurement of DC, CV and noise characteristics, enabling MPI users easy access to the most accurate ProPlus SPICE modeling and noise characterization offerings. The advanced probing technologies developed by...
Cadence-Sponsored Event will be held December 7 in San Jose, Calif.
SAN JOSE, CALIF. –– November 14, 2017 –– Oski Technology, Inc., the established and trusted leader in Formal verification methodology expertise, today announced that Barefoot Networks, Cavium, and Qualcomm will share their Formal Verification experiences at the next Decoding Formal Club Meeting.
Sponsored by Cadence Design Systems, it will be held at The Conference Center in San Jose, Calif., Thursday, December 7. The event will close out this year’s speaking engagements and will follow the Oski Expert Talks given at Cadence’s Jasper User Group and Formal Club conferences in San Jose, Calif.; Bracknell, U.K.; and Sophia-Antipolis, France.
The keynote address will be delivered by Dan Lenoski, vice president of...
Programmable Product Platform, Technology Innovator Verific Customer Since 2014
ALAMEDA, CALIF. –– October 11, 2017 –– Verific Design Automation today announced Efinix™, an innovator in programmable product platforms and technology, selected its Verilog Parser Platform and register transfer level (RTL) elaborator to serve as the front end to the Efinity™ Integrated Design Environment (IDE).
A Verific customer since 2014, Efinix is accelerating market deployment of its Quantum™ programmable technology for deep learning and compute acceleration applications. The technology delivers a 4X Power-Performance-Area (PPA) advantage over traditional programmable technologies.
“Verific has been with us for every step of the development process,” notes Sammy Cheung, co-founder, chief executive...
Sets Goals to Increase WWED’s Visibility, Promote Vibrant, Supportive Community of Women within Semiconductor Industry
SAN JOSE, CALIF. –– October 4, 2017 –– McKenzie Ross, marketing communications manager for OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), will reprise her role as chair of the Worldwide Women in Electronic Design (WWED) Steering Committee for 2017–2018.
Ross has led the WWED Steering Committee since 2016 and served as vice chair in 2015. In addition to selecting and promoting a female speaker for the Design Automation Conference (DAC), the steering committee works to increase WWED’s visibility and promote a vibrant, supportive community of women within the semiconductor industry...
SystemVerilog, Verilog Parsers Function as PowerBaum Power Analysis’ Front End
ALAMEDA, CALIF. –– September 26, 2017 –– Baum, a leader in power analysis solutions, today became the newest licensee of Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry.
Under terms of the agreement, Verific’s SystemVerilog and Verilog parsers function as the front end to the recently launched PowerBaum from Baum. PowerBaum provides fast and accurate power models to enable system-level power analysis for an entire system-on-chip (SoC) design with realistic scenarios.
“We contacted Verific as soon as our product development got under way because they are the gold standard in...
Renowned Decoding Formal Club Meeting to be hosted September 26 at New Office
SAN JOSE, CALIF. –– September 19, 2017 –– Oski Technology, Inc., the leader in formal verification methodology and services, today officially opened its new corporate headquarters in San Jose, Calif.
The move to the expanded space is prompted by the increased demand for Oski’s verification expertise and training in solving complex design issues and the desire for a more centralized location to its Silicon Valley-based customers. The new facility will be inaugurated at Oski’s next Decoding Formal Club Meeting sponsored by Cadence Design Systems Tuesday, September 26.
“Our engineering and support group has grown consistently over the last several years as formal verification becomes a mainstay...
Rengarajan Will be Responsible for Driving Evolution, Adoption of Functional Safety Suite, Managing Strategic Business Initiatives
AUSTIN, TEXAS –– September 6, 2017 –– Srikanth Rengarajan, former associate director at Broadcom, today joined Austemper Design Systems, supplier of an end-to-end Functional Safety Tool Suite for system-on-chip (SoC), application specific integrated circuit (ASIC) and intellectual property (IP) designs, as vice president of products and business development.
In his new role, Rengarajan will be responsible for driving adoption of a tool-driven discipline and end-to-end automation for mission-critical, functional safety applications. He also will manage business relationships with semiconductor and electronic design automation (EDA) companies...
Leverages Austemper’s Early Success in Automotive Applications
AUSTIN, TEXAS –– September 19, 2017 –– Austemper Design Systems, supplier of a comprehensive Functional Safety Tool Suite for system-on-chip (SoC) designs, today announced it opened sales channels in the U.S., Europe and Japan and appointed sales executives to manage each region.
Denny Watts and John Copponi of EDJE Technology from Massachusetts will be responsible for the Eastern Region sales efforts, while Sanjay Bombwal of Saphirus Inc. will represent Austemper in California. Willi Ahnen and Robert Eichner of Munich-based EuropeLaunch will manage European sales and Atsushi Ishii will direct Far East sales in Tokyo, Japan.
All report to Srikanth Rengarajan who recently joined Austemper as vice president of...
Winning Entry from Nokia’s Wolfgang Roessel, Runners Up from Infineon, ARM
SAN JOSE, CALIF. –– July 27, 2017 –– OneSpin® Solutions, provider of innovative formal verification solutions for highly reliable, digital integrated circuits (ICs), today announced Wolfgang Roessel of Nokia provided the winning entry to OneSpin’s Einstein’s Riddle challenge, based on a public poll of the top 10 solutions.
Runners up are Darren Galpin from Infineon, Laurent Arditi at ARM and Phani Kumar Peri of Infineon.
OneSpin issued a challenge to solve the classic Einstein’s Riddle using any formal verification tool. Entries were narrowed down to 10 and OneSpin confirmed they executed correctly using its DV-Verify™ formal verification. Members of the semiconductor industry voted for their...