Along with Leti, List Will Demonstrate New Toolchain Solution
For Protecting Software Against Physical Attacks
GRENOBLE, France – June 14, 2017 – Leti, a research institute of CEA Tech, will present a keynote address on embedded systems and the “Challenges of the Emerging IoT Security Arena” at DAC 2017, the design automation conference at the Austin, Texas, Convention Center, June 18-22.
At a time when the traditional world of embedded systems’ security is meeting the world of consumer electronics, the security and privacy constraints on the Internet of Things are stringent. Frequent attacks exploit objects’ security weaknesses by targeting the objects themselves, or associated systems and services, as well as the end users. The survival of this young industry...
Nolam IP cores for MIL-STD 1553, ARINC-429, and ARINC-825 are field-proven and DO-254 compliant
WOODCLIFF LAKE, NJ USA — June 1, 2017 — Semiconductor IP provider CAST, Inc. today announced a new partnership with Nolam Embedded Systems, and the resulting availability through CAST of several Nolam avionics
related IP cores.
Nolam Embedded Systems is a successful developer and integrator of real-time embedded systems. The company provides IP, board-level, and complete integrated system products, and primarily serves the aerospace, defense naval and aerospace, and industrial markets.
The partnership initially focuses on adding three Nolam IP cores for avionics standards to the CAST product line:
• The MIL-STD 1553 core is a serial data bus controller for avionics, space,...
WOODCLIFF LAKE, NJ USA — May 16, 2017 — Novatek Microelectronics Corp., a customer of semiconductor IP provider CAST, Inc., has applied a data decompression IP core to achieve a major consumer benefit: significantly reduced start-up delay in digital televisions.
Consumers don’t like to wait when they turn on a television set. Much of this start-up or “boot time” delay is due to the time required to read the initial firmware code out of the relatively slow, non-volatile, flash memory where it is stored. Novatek’s innovation dramatically reduces this boot time by storing a much smaller, compressed version of the firmware, and using a fast hardware decompression engine obtained from CAST to rapidly decompress the code during boot.
The ZipAccel-D GUNZIP/ZLIB/Inflate Data...
New IEEE 802.1AS AVB/TSN and SENT/SAE J2716 Cores now available;
CAN/CAN-FD Controller Core now supports AUTOSAR-compliant time-stamping
WOODCLIFF LAKE, NJ USA — June 13, 2017 — Semiconductor intellectual property provider CAST, Inc. today announced three significant improvements to its automotive IP family:
• A new IEEE 802.1AS Hardware Protocol Stack Core works with any eMAC (Ethernet Media Access Controller) to enable easy development of time-aware nodes for
standard AVB/TSN (Audio Video Bridging/Time Sensitive Networking) networks. This serves a variety of audio/visual and industrial applications, and is essential for the growing use of Ethernet to connect diverse automotive systems.
• A new, full-featured SENT/SAE J2716 Controller Core serves as a transmitter and/or...
Rapid Application Development Platform will be added to Verific’s Parser Platform
ALAMEDA, CALIF. –– June 12, 2017 –– Verific Design Automation, the recognized leader of SystemVerilog, VHDL and UPF Parser Platforms in production and development use throughout the semiconductor industry, today announced it acquired the INVIO product line from Invionics Software.
Under terms of the agreement, Verific will acquire Invionics Software’s entire INVIO technology portfolio for electronic design automation (EDA) tools and flows. An R&D group with real-world design experience and a deep understanding of EDA software development will join Verific’s engineering department.
The move enables Verific users to simplify and streamline their design environment, while reducing cost and...
Platform Leverages Growing Use of IP, Addresses Higher Levels of Design Automation, Need for Collaboration
AUSTIN, TEXAS –– June 6, 2017 –– Concertal™ Systems will demonstrate a cloud-based System Design Automation (SDA) platform for designing and simulating new system-on-chip (SoC), application specific integrated circuit (ASIC), and field programmable gate array (FPGA) designs at the Design Automation Conference (DAC) in Booth #1421.
“Design complexity, development costs and time-to-market demands are more challenging than ever, driving the need for rapid exploration and higher levels of design automation and verification,” says Bob Ledzius, founder and chief executive officer of Concertal. “With over 25% of new designs now containing more than 50-million gates, SDA...
IP Guru Will Answer DDR Questions at DAC Booth; Uniquify “Stars of IP” Sponsor
SAN JOSE, CALIF. –– June 7, 2017 –– Uniquify, a leading system-on-chip (SoC) fabless manufacturer and DDR memory system intellectual property (IP) provider, today announced that its LPDDR4 Super Combo IP for the 28-nanometer (nm) low-power semiconductor process node is in volume production.
The patented silicon-proven IP breaks the performance barrier by delivering up to 3200 Megabits per second (Mbps) per pin performance for mobile LPDDR4 DRAM. It is the industry’s first IP solution to achieve multi-GHz performance in the 28nm node, while a flexible configuration supports other DDR combinations, such as DDR3/4 and LPDDR2/3.
Uniquify’s Super Combo DDR IP subsystem includes controller, PHY and I/O...
Longtime DAC Sponsor Hosts Variety of Events Again This Year
REDWOOD CITY, CALIF. –– June 6, 2017 –– The Electronic System Design Alliance (ESD Alliance), an international association of companies providing goods and services throughout the semiconductor design ecosystem, celebrates the month of June and the start of the Summer Solstice at two leading semiconductor events.
It will exhibit at the sixth annual Global Semiconductor Alliance (GSA) Silicon Summit Wednesday, June 14, from 8 a.m. until 3 p.m. in Mountain View, Calif. Attendees who stop by the ESD Alliance booth will be able to meet Executive Director Bob Smith and learn about its programs, initiatives and current trends in the industry.
The following week, the semiconductor design ecosystems heads to...
Will Exhibit in Verific’s DAC Booth, Setting the Stage for Launch of High-Speed, Accurate Power Analysis and Modeling Solutions
DAEJEON, KOREA –– JUNE 7, 2017 –– Baum today announced its plans to provide electronic design automation (EDA) software and solutions that will enable engineering groups to fully optimize the energy efficiency of their semiconductor designs.
As the emerging power solutions expert, Baum will launch in September a state-of-the-art, high-speed and accurate power analysis and modeling solution initially targeting the automotive, internet of things (IoT), mobile, networking and server markets.
Baum representatives will be available to answer questions about its power analysis and modeling solution and give demonstrations from 1 p.m. until 3 p.m. daily...
First-Time DAC Exhibitor Will Demonstrate Portfolio of Machine Learning-Based Tools
SINGAPORE –– JUNE 6, 2017 –– Plunify®, supplier of field programmable gate array (FPGA) timing and performance software based on machine learning techniques, today introduced Kabuto™ to minimize and eliminate performance errors.
Kabuto joins Plunify’s InTime™ for time closure and performance optimization to solve critical design problems for a variety of markets, including data center, advanced driver assistance systems and high-frequency trading. “Our machine learning features for timing closure and optimizing FPGA designs enables our users to outperform their competitors,” remarks Harnhua Ng, Plunify’s chief executive officer and co-founder.
Plunify will exhibit at the Design Automation...