Bypass logic verification is a common and difficult challenge for modern VLSI design that arises in the verification of CPU, GPU, and networking ASICs. Get it wrong and/or miss a bug in the bypass logic and whole system can simply freeze.
Fortunately, the 2012 DAC User Track Best Presentation award-winning paper titled "Deploying Model Checking for Bypass Verification" by engineers from Cisco and Oski Technology (full citation below) describes an easily replicated, nearly push-button flow that does not require users to put in a lot of effort to write complex input constraints. And full disclosure: they used my favorite combined simulation+formal tool, Incisive Enterprise Verifier (IEV)!
There are three reasons why DAC will be spectacular come June in Austin: It’s the 50th instantiation of the conference; for the first time ever DAC is coming to the home of Office Space; and Synopsys Solutions Group Chief Architect Yervant Zorian will be General Chair, which means the 2013 Design Automation Conference has got the very best in the business at the top, a guy who’s CV includes leading committees of all shapes and sizes, IEEE Standards initiatives, and a variety of conferences, big and small.
Full Article - Peggy Aycinena, EDACafe
Aspera develops software transfer technologies to achieve performance and cost savings using existing network infrastructure. They also provide engineering services to implement their products and transfer technology in small to large business enterprises. I expect them to be showing how they can help multinational engineering teams to share design data and keep track of all it in a globally distributed environment.
ChipStart is an IP developer focusing on solutions such as SoC System Manager (SSM); custom embedded Memory products; and Voltage Regulators. They are also an IP Aggregator. They have IP partners working with them to create a larger potential for pre-integrated IP.
DXCorr Designs is focused on providing embedded solutions for foundation IP,...
Several weeks ago, I asked companies to send me information about the demos that would be showing at DAC this year. I am pleased to say that many companies responded. I hope you find this better than another list of what you must see at DAC, instead, you can be guided by some real information that may actually be helpful in planning your trip around the show floor. Companies that did not get information to me, feel free to add your information by placing a comment on this article.
Gary Smith, the dean of EDA analysts, has his sights set on two major trends he thinks will be prominent at this year's Design Automation Conference.
"The big thing at DAC this year is debug," said Smith, chief analyst at his own eponymously named firm, Gary Smith EDA. "We are debugging everything now."
Smith, who will be kicking off his 19th DAC with his annual state of EDA update on Sunday (June 3) at 7 p.m. at the Marriott Hotel in San Francisco, counts seven vendors offering some form of debug: EVE, Cadence, Mentor, SpringSoft, Axiom, Vennsa and IC Manage. "That is the hottest thing at DAC," Smith said.
Breaking your products so your customers won't have to.
Thoughts on hardware verification, the EDA industry, and related topics from the perspective of JL Gray, a verification consultant at Verilab.49th DAC: Day 1 Highlights
The 49th Design Automation Conference kicked off yesterday evening with a reception and a presentation by Gary Smith. One of the themes of Gary's talk was his observation that a phenomenon he termed "multi-platform design" was allowing chips to be designed for approximately $40M, as opposed to the $75M he had predicted last year. Part of the reason for the reduction in cost was, in his view, based on a significantly increasing use of ESL techniques (especially on the modeling and verification side of things...
Despite several glitches along the way, the semiconductor industry has managed to move down the process technology curve as defined by Moore’s Law. But going forward, the industry will require new breakthroughs in chip-scaling and EDA technology to enable the next wave of systems over the next decade, according to a technologist from ARM Ltd.
During and after a keynote address at the Design Automation Conference (DAC) in San Francisco on Tuesday (June 5), Mike Muller, chief technology officer at ARM, also addressed a range of other topics, including the state of the foundry industry, the demise of PCs, and, of course, the mobile revolution based on ARM’s technology.
It’s time to start examining the Conference Program and figure out how you’re going to spend your time in the first week of June when you’re attending the Design Automation Conference next month in San Francisco at Moscone Center.
Super Sunday …
Sunday is never a Day of Rest for DAC attendees, and Sunday June 3, 2012 is no exception. First, there are 4 co-located conferences happening in Moscone Center on DAC Sunday:
* IWLS: International Workshop on Logic Synthesis
* SLIP: System Level Interconnect Prediction Workshop
* HOST: IEEE Internt’l Symposium on Hardware & Trust
* ESLsyn: Electronic System Level Synthesis Conference
There are also 7 DAC-related workshops:
* CMOS Design at 60 GHz & Beyond
* Moore than More...
Why call this Thermocouple Thursday?
For two reasons. First, because the rest of the days at DAC 2012 in San Francisco got alliterated:
* Super Sunday
* Marvelous Monday
* Terrible Tuesday
* Wicked Wednesday
And second, because “a thermocouple is a device consisting of two dissimilar metals joined at two points, the potential difference between the two junctions being a measure of their difference in temperature.”*
And if that doesn’t describe Thursday, June 7th, at DAC 2012 what does?
After all, nobody really sticks around for Thursday at DAC unless a) they’re presenting on that day, b) they’ve got a client and/or student presenting on that day, or c) they’re staying through the weekend to vacation in The City.
But people not...
For more than a decade embedded systems developers have looked with hope and optimism at the emergence of hardware description languages such as C++ derived System C, C-derived Verilog, Ada-derived VHDL, and the various EDA tools for simplifying hardware/software co-design, co-verification, and emulation. Typical of that early optimism is “The architecture exploration process,” written by Lloyd Pople in 2000. That optimism has continued in morerecent design articles, white papers, and webinars on these topics, of which myEditor’s Top Picks are:
Use emulation to debug SW/HW at the same time by EVE-USA’s Donald Cramb
Expand emulation’s reach with virtual devices by Mentor Graphics’ Jim Kenney
HW/SW co-verification basics, a four part...