It has been an unusual DAC this year, as the show went virtual due to the Covid-19 pandemic. There was no exhibition floor as such, but there was a comprehensive programme of keynote speeches, presentations, tutorials and panel discussions.
There was a lot of activity around RISC-V, including a presentation by Imperas Software (www.imperas.com) entitled What’s Next for RISC-V? Vectors, Verification, and Value-added Extensions. During the event, the company announced that its RISC-V reference models have been implemented by the OpenHW Group to establish the Core-V processor verification test bench which will validate open source cores for the open source community.
Full article: Caroline Hayes, ElectronicsWeekly.com