Research Manuscript Submissions

The Design Automation Conference (DAC) is the premier event to showcase cutting-edge research achievements in the design and design automation of electronic circuits and systems. In addition to a broad range of topics within the domains, Design, EDA, Embedded Systems & Software (ESS), Machine Learning/AI, Security as well as Autonomous Systems and IP, the 2020 edition of DAC is expecting particular interest in DES3.Approximate Computing for AI/ML, DES4.AI/ML System Design, ESS5 Time-Critical System Design and security (SEC1-3) that have been extended and/or redesigned to reflect recent trends. Acceptance rates for manuscript publication are uniform across all topic areas and they have been hovering between 20%-25% for the past several years.

Submission Format

Stage One: Abstract Submission

A title, abstract (approximately 100 words), and a list of all co-authors must be submitted by November 21, 2019 (5:00pm MT (-07:00 GMT)). You may also submit the manuscript at this time.
Authors will be asked to report Conflicts of Interest with TPC members. View more details in the "Conflict of Interest" tab at the top of this page.

Stage Two: Manuscript Submission

The paper itself (up to 6 pages including all references) is due by November 27, 2019 (5:00pm MT (-07:00 GMT)). Each submitted manuscript must discuss original work that has not been previously published in other indexed research databases.

Authors are responsible for ensuring that their manuscript meets the submission guidelines outlined in the tabs at the top of this page. There will be no opportunity for re-submission to correct any issues.

Your manuscript will be reviewed as a finished manuscript. Preliminary submissions will be at a disadvantage.

SUBMISSION TIMELINE

Submission Opens - October 1, 2019

Abstract Deadline - November 21, 2019

Manuscript Deadline - November 27, 2019

Accept/Reject Notification - February 28, 2020

Proceedings Manuscript Deadline - April 7, 2020

Submission Rules (Abstract & Manuscript)

A submitter must enter the names, affiliations, cities, states, countries and email addresses of ALL the co-authors. The addition of new co-authors will not be permitted after November 27.
DO NOT identify the author(s) by their name(s) or affiliation(s) anywhere on the manuscript or abstract, with all references to the author(s)' own previous work or affiliations in the bibliographic citations being in the third person. Avoid the use of “omitted for blind review” in the bibliography section. Make sure the PDF metadata does not contain the author information.
The abstract of approximately 100 words must clearly state the significant contribution, impact, and results of the manuscript.
The manuscript must be within up to 6 pages including all references, double-columned, 9 or 10-pt font, in PDF format only, be a readable file and follow the IEEE style template. The length and content of the submitted version and that of the final version (if accepted) should not be significantly different.
A submitter is required to check the conflicts of interests (COI) field and the duplicate submission field. See the "Conflict of Interest" tab and the "Duplicate Submission" section for further information.
An author of each accepted submission is required to:
- Produce a paper for the official conference proceedings.
- Make sure the final manuscript to be published passes the IEEE eXpress compliance check.
- Sign and submit a copyright form
In addition:
Following IEEE's policy on authorship, anyone listed as Author on a paper must meet all the following criteria:
- They have made substantial intellectual contributions to some components of the original work described in the paper; and
- They have participated in drafting and/or revision of the paper; and
- They are aware that the paper has been submitted for publication; and
- They agree to be held accountable for any issues relating to correctness or integrity of the work

Duplicate Submissions

DAC adheres to strict rules regarding duplicate submissions. Submissions must be clearly novel and distinct with respect to other submissions to DAC 2020, concurrent submissions to other conferences and previously published work.
- All closely related work should be properly referenced. If such related work is authored by one of the co-author(s) of the manuscript in submission, it should be referenced as if it were written by others.
- Any extended version of the submitted manuscript should not be submitted or under review before the formal notification of the DAC ‘s review decision.
- If any co-author has any paper that may be perceived as having overlapping contributions and that is simultaneously under review by another venue, such papers must be disclosed in the submission process.
Submissions which fail to follow the above guidelines will be automatically rejected. In serious cases, the authors’ names will be reported to IEEE and kept in records, as well as sent to the Technical Chair or the Editor of the venue where the duplicate manuscript was submitted; the authors may be banned from publishing at future DAC conferences.

Disclosure Process for Unpublished Work

When submitting to DAC, authors face a dilemma. DAC has a blind review process in which the author’s identity remains anonymous. However, the submission rules compel the authors to cite relevant publications that have already been accepted or are under review by another conference (such as ICCAD, DATE, ASP-DAC, etc.). Disclosing these papers under the citation list reveals the authors’ identities. To circumvent this issue, DAC has implemented a disclosure process.

When submitting a paper, the authors are asked to list each relevant paper that has not yet been published and include the corresponding pdf of the paper. The TPC Chair will be able to check for self-plagiarism and relevance without revealing the author identities to the reviewers. Failure to disclose such papers will be considered as omission of closely related work and subject to the same penalties outlined in the Duplicate Submissions, as discussed in the section.

CONFLICT OF INTEREST

To further strengthen the review process, each submitter is asked to identify any Technical Program Committee (TPC) members with whom s/he has conflict of interests (COI). The TPC list is available below.

An author has a conflict with a member of the Technical Program Committee if one or more of the situations below holds:

Advisor-advisee relation
Co-authors of a paper (published and/or under review) in the last 24 months
Author and TPC member are from the same institution
Co-PIs of a grant in the last 2 years
Close personal or family relationship

The submitter should indicate the COIs of all authors with members of the Technical Program Committee upon submission. Failure to do so may lead to automatic rejection of the submission. If the submitter marks members of the Technical Program Committee as CoI where there is in fact no CoI, that may also lead to automatic rejection.

Frequently Asked Questions

How should I submit a research manuscript?

Authors are asked to submit their work in two stages. In stage one (Abstraction Submission), a title, abstract, and a list of all co-authors must be submitted via the DAC web-submission site. In stage two (Manuscript Submission), the manuscript itself is submitted. Authors are responsible for ensuring that their manuscript submission meets all guidelines, and that the PDF is readable. To ensure fairness for all submitters, there will be no grace periods to fix problematic submissions.
Authors are to submit a 6 page manuscript. The manuscript should stand on its own, with references in the last page of the 6-pages manuscript. Authors are responsible for ensuring that their manuscript meets the manuscript guidelines of the IEEE style template, including font size, line spacing, etc. There will be no chance of resubmitting to correct any issues.
In addition, authors should make sure to fulfill the conflict of interest rules as specified in the "Conflict of Interest" tab at the top of this webpage.

How should I submit the conflict of interest (COI) information?

Submitters should report COIs of all co-authors with respect to members of the Technical Program Committee upon submission. However, it is recommended that submitters work on marking COIs as soon as they submit their manuscript's abstract, since this task may require some time, which is often scarce in the final sprint towards the completion of a manuscript's submission. Modifications to marked COIs can be made any time prior to the manuscript deadline.

Authors are asked to mark all the TPC members who have COIs with at least one of the authors at the time of abstract registration. Do not mark any members of the Technical Program Committee as CoI where there is in fact no CoI.

What if authors failed to identify TPC members with whom they have a conflict of interest?

DAC assumes that authors have no additional COIs with TPC members, beside those that have been declared at the time of manuscript submission. If a manuscript is found to have failed in identifying a COI, during or after the paper selection process, the submitted manuscript will be automatically rejected. Same hold if members of the Technical Program Committee are marked as CoI where there is in fact no CoI.

What is the DAC research manuscript timeline?

DAC will follow the timeline below in processing, selecting and publishing research manuscripts:

October 1 to November 27: Research submission site is OPEN.
- November 21: Research abstract submissions are DUE by 5:00pm MT (-07:00 GMT)
- November 27: Research final manuscript submissions are DUE by 5:00pm MT (-07:00 GMT)
The second week in February: A list of accepted manuscripts will be posted on the DAC website.
February 28: Accept/reject notices and confirmation forms will be emailed to authors.
March 6: Accepted papers must submit confirmation forms.
March 26: Accepted papers must submit copyright forms.
March 28: Speakers will receive final paper submission details and instructions.
March 31: The technical program will be live on the DAC website.
April 7: Final manuscript is DUE to the proceedings publisher by 5:00pm MT (-07:00 GMT).
April 10: Speaker registration deadline. One author from each manuscript is required to register at the $510 speaker registration rate.
June 25: Speaker bio and draft slides due for review.
July 1: Session Chairs will provide feedback to speakers regarding their draft presentation slides.
July 9: Final presentation slides are due for the DAC archive.
July 19: The Design Automation Conference begins! Please visit the Research Speaker Resource Center for more details on important dates and actions for accepted papers.

Which category should I select when I submit my manuscript?

The Call for Contributions lists several categories; please select the most appropriate primary topic when submitting your abstract. Authors of submissions that cover cross-cutting topics should select a category that is closest to the essential contribution of the submission. Submissions will be asked to select a broad category (ex. “EDA1. System-on-chip and HW/SW Codesign. A complete list of available categories and topic areas can be found in the CFP. Please note that their separate categories for electronic design automation topics, embedded systems and software topics, autonomous electronic design, design and system security, and electronic design topics.

If my work is mainly about design, should I submit it to the regular research track or the Designer or IP Tracks?

The research track at DAC 2020 will include a DESIGN (DES) focus to feature high-quality contents on design research, design practices, and design automation for cross-cutting topics.

If you think that your work makes a significant contribution to any of the design related topics, you should consider writing a complete 6-page research manuscript and submit it to the regular research track. On the other hand, if your work is more of a design practice using EDA tools or if you cannot meet the research manuscript deadline, you can consider submitting your work to the Designer Track or IP Track, which do not require a manuscript and entail no publication.

Six pages only, or is additional supplemental material allowed?

All submissions to the Research Track are subject to the six-page limit. No additional supplemental material is allowed.

How do I avoid referencing my own work to ensure the integrity of the blind review process?

To satisfy the criteria for a blind review process, the Call for Contributions states that any references to the author(s) own previous work or affiliations in the bibliographic citations must be in the third person. For the blind review process, DO NOT LIST THE NAMES OR AFFILIATIONS OF ANY OF THE AUTHORS ANYWHERE ON THE MANUSCRIPT, except in the references section (if citation to prior work is required).

Example: A. and B. presented a method for listing self-referential citations in [5]. 
[5] A. A and B. B, How to write a research DAC paper, 2020.
DO NOT use “omitted for blind review” to cite authors’ own papers. Describe all related papers published by you as if they were written by others.
Citation of authors’ unpublished papers is not allowed, including citation of potential double and/or simultaneous submissions. If this situation arises, submitters must follow the disclosure requirements to disclose their (or thier co-authors) related work that is under review or accepted for publication.

I submitted a longer version of my manuscript to another conference/journal. Can I still submit it to DAC?

DAC adheres to strict rules regarding double and/or simultaneous submissions. No new technical content should be under review during any time overlapping with DAC's selection and publication of manuscripts. In general, an extended version of the conference paper should be submitted to a journal after the first day of the conference. Your submissions must be clearly distinct from any other submissions under review. Use your judgment. If in doubt, consult with a more senior colleague. Double submissions are unethical, and a serious issue within the IEEE community.

How do I disclose a paper under review or an accepted but not published paper?

When submitting a paper, the authors are asked to list all potentially relevant papers that have not yet been published and provide an electronic copy (in pdf format) of those papers. The TPC Chair will be able to check for self-plagiarism and relevance without revealing author identities to the reviewers. Failure to disclose such papers will be considered as omission of closely related work and subject to the same penalties outlined in the "Duplicate Submissions" tab.

Can a paper that has been uploaded to arXiv be submitted to DAC?

The DAC publication policy does allow for papers published on arXiv to be submitted to DAC. Note, however, that the authors are expected to follow all reasonable efforts to ensure that the DAC submission iscompliant with the double-blind review process.

What makes a good DAC manuscript?

DAC Electronic Design Automation (EDA) research manuscripts have at their core novel algorithms or novel algorithm implementations for important problems facing leading edge electronic design automation. These may address the problem at any level of abstraction (from high-level blocks down to the bare transistor). They can cover both design implementation (for example, physical layout or logic synthesis) and design analysis (for example, signal integrity analysis, rule checking, functional verification, and circuit simulation).

DAC Embedded Systems and Software (ESS) research manuscripts cover novel advances in embedded systems software and hardware, from the very highest levels of system specification (e.g., domain-specific languages and model based design) to hardware/software implementations of embedded systems, their associated software design tools and architectural platforms, as well as validation, verification, and reliability. ESS topics will also cover modeling, optimization, and exploration of multiple embedded system constraints (e.g., reliability, power, security). ESS case studies, platforms and design methodologies are also an integral part of these topics.

DAC Design (DES) research manuscripts feature high-quality contributions on design research, design practices, and design automation for cross-cutting topics, ranging from systems and architectures, particularly specialized solutions to embedded systems, storage and memory structures.

DAC Security (SEC) research manuscripts span topics relating to embedded systems, cross-layer and hardware security, applied to all the layers of the hardware stack, from devices to architectures. The nature of the manuscripts range from attacks, to protection mechanisms and metrics.

Finally, DAC Autonomous electronic design (AS) research manuscripts discuss autonomous system design tools and methodologies.

Can I submit as a Work-in-Progress (LBR) presentation if my paper is not accepted as a research manuscript?

If the TPC subcommittee does not accept your manuscript as a research manuscript at DAC, they will also determine if your submission meets the requirements for a WIP presentation and invite WIP-eligible manuscripts to present during a specific poster session at DAC. Note that WIP presentations papers are not published in the DAC proceedings. Thus, in this situation, you do not need to re-submit your manuscript to the WIP submission site.

You may also submit other distinct works directly through the LBR submission site. The LBR submission deadline is March 5, 2020. Please see the Late Breaking Results section in the Call for Contributions for more details.

I still have some questions. Who do I contact?

For additional information, please contact Joerg Henkel, the 57th DAC Technical Program Chair.

Submission Categories

Authors of research manuscripts are required to specify main category from the list below. Authors of submissions that cover cross-cutting topics should select a category that is closest to the essential contribution of the submission. Your selection should take into consideration the likely expertise of the group of people who will serve in reviewing manuscripts for each category.

AUTONOMOUS SYSTEMS

AS1. Autonomous Systems (Automotive, Robotics, Drones)

AS1.1 Autonomous Systems Design Tools and Methodologies
AS1.2 Autonomous Systems Architectures
AS1.3 Autonomous Systems Safety and Reliability

DESIGN

DES1. Design of Cyber-physical Systems and IoT

DES1.1 Cyber-physical systems and Internet-of-Things (IoT) platforms
DES1.2 Low-power and energy-efficient design techniques for IoT
DES1.3 Partitioned Edge/hub/cloud processing
DES1.4 Dependable and safety-critical embedded system design
DES1.5 Networking and storage system design
DES1.6 Advanced wireless communication system design
DES1.7 Machine Learning for Cyber-Physical Systems

DES2. SoC, Heterogeneous, and Reconfigurable Architectures

DES2.1 Architectures for stochastic, statistical and approximate computing
DES2.2 SoC and heterogeneous multi- and many-core architectures
DES2.3 Run-time and design-time reconfigurable processor architectures

DES3. Approximate Computing for AI/ML

DES3.1 Quantization, Pruning and Model Compression
DES3.2 Approximate and Stochastic hardware for AI/ML
DES3.3 Cross-layer approximations and accuracy tradeoffs in AI/ML

DES4. AI/ML System Design

DES4.1 HW and system architectures for neural network training and inference
DES4.2 Architectures for emerging AI/ML algorithms (beyond neural networks)
DES4.3 AI/ML Architectures with Beyond-CMOS technologies
DES4.4 Software frameworks and libraries for AI/ML
DES4.5 Automating AI/ML system design (AutoML)

DES5. Emerging Models of Computation

DES5.1 Biologically-based or biologically-inspired computing systems
DES5.2 Design automation for system & synthetic biology
DES5.3 Neuromorphic and brain-inspired computing
DES5.4 Quantum computing

DES6. Digital and Analog Circuits

DES6.1 2.5-D and 3-D integrated circuit designs
DES6.2 Clock network and interconnect designs
DES6.3 Low-power and energy-efficient digital circuits
DES6.4 Analog, mixed-signal and RF circuits
DES6.5 Circuits for advanced wireless communication
DES6.6 Memory design

DES7. Emerging Device Technologies

DES7.1 New transistor structures, beyond-CMOS devices (e.g., steep-slope devices, spintronics), and new process technologies
DES7.2 Nanotechnologies, nanowires, nanotubes
DES7.3 Emerging non-volatile memory devices
DES7.4. New Architectures with Emerging Technologies

EDA

EDA1. System-on-Chip Design Methodology

EDA1.1 System-on-Chip (SoC) specification, modeling, analysis, simulation, and verification
EDA1.2 Application-specific processor design tools
EDA1.3 Design tools for accelerator-rich architectures and heterogeneous multi-cores
EDA1.4 Tools for reconfigurable computing
EDA1.5 HW/SW co-design, interface synthesis, and co-verification
EDA1.6 System-level methods for reliability and aging

EDA2. In-Package and On-Chip Communication and Networks-on-Chip

EDA2.1 Communication architecture modeling and analysis
EDA2.2 Synthesis and optimization of communication architectures
EDA2.3 NoC architectures and design methodologies
EDA2.4 Communication architectures using alternative technologies (e.g., nanophotonics, RF, 3D, etc.)

EDA3. Cross-Layer Power Analysis and Low-Power Design

EDA3.1 System-level low-power design analysis and management
EDA3.2 Architectural power reduction techniques and analysis tools
EDA3.3 Low-power circuit design methods and tools
EDA3.3 Low-power circuit design methods and tools
EDA3.4 System-level and architectural thermal analysis and management

EDA4. RTL/Logic Level and High-level Synthesis

EDA4.1 Combinational, sequential and asynchronous logic synthesis
EDA4.2 Technology mapping, cell-based design and optimization
EDA4.3 High-level, behavioral, algorithmic, and architectural synthesis, “C” to gates tools and methods
EDA4.4 Synthesis for FPGAs
EDA4.5 Synthesis for circuits in emerging device technologies
EDA4.6 Machine Learning techniques for synthesis

EDA5. Analog Design, Simulation, Verification and Test

EDA5.1 Analog, mixed-signal, and RF design methodologies
EDA5.2 Automated synthesis and optimization of analog designs
EDA5.3 Analog, mixed-signal, RF, electromagnetic, substrate noise modeling and simulation
EDA5.4 Model order reduction techniques for analog/RF designs

EDA6. Digital Design, Timing and Simulation

EDA6.1 Timing analysis and simulation/delay modeling
EDA6.2 Power/signal integrity analysis and simulation
EDA6.3 Process technology modeling
EDA6.4 Circuit- and gate-level power/thermal analysis

EDA7. Physical Design and Verification, Lithography and DFM

EDA7.1 Floorplanning, partitioning, placement
EDA7.2 Interconnect and clock network planning and synthesis
EDA7.3 Cross-layer placement and routing optimization for timing/power/yield
EDA7.4 Post-Layout and post-silicon optimizations
EDA7.5 Physical design of 3-D integrated circuits
EDA7.6 Reticle enhancement, lithography-related design optimizations and design rule checking
EDA7.7 Design for manufacturability, yield, defect tolerance, cost issues, and DFM impact
EDA7.8 Machine Learning Techniques for Physical Design

EDA8. Design Verification and Validation

EDA8.1 Functional and transaction-level modeling and validation, coverage and test generation for hardware and embedded systems
EDA8.2 Emulation and hardware acceleration
EDA8.3 Formal and semi-formal verification and verification technologies
EDA8.4 Verification of firmware, software, and hybrid hardware/software systems
EDA8.5 Machine learning techniques for verification
EDA8.6 Post-silicon design validation and debug

EDA9. Manufacturing Test and Reliability

EDA9.1 Fault modeling, ATPG, DFT, BIST, compression
EDA9.2 Memory, FPGA and emerging technology test and reliability
EDA9.3 SoC, board- and system-level test
EDA9.4 Post-silicon test and defect diagnosis
EDA9.5 Analog/mixed-signal/RF verification and test
EDA9.6 Noise, aging induced delays, and reliability analysis

ESS

ESS1. Embedded Software

ESS1.1 Embedded software verification methodologies
ESS1.2 Embedded operating systems, middleware, runtime support, resource management, and virtual machines
ESS1.3 Software techniques for multicores, GPUs, and multithreaded embedded architectures
ESS1.4 Compilation strategies, code transformation and parallelization techniques for embedded systems
ESS1.5 Domain-specific embedded libraries (e.g., for machine learning)
ESS1.6 Embedded Software Development Case Studies (e.g., ANDROID development, ARM-based systems, etc.)
ESS1.7 Operating Systems and Middleware
ESS1.8 Software Design and Analysis

ESS2. Embedded System Design Methodologies

ESS2.1 Embedded system specification, virtual prototyping and simulation
ESS2.2 Embedded system synthesis and optimization
ESS2.3 Analysis of embedded system QoS metrics - performance, battery life, reliability, etc.
ESS2.4 Design methodologies for self-aware, self-adaptive and autonomous embedded systems
ESS2.5 Design methodology for mobile, wearable and Internet of Things devices
ESS2.6 Machine Learning for Embedded Design Methoidologies

ESS3. Embedded Storage and I/O Systems

ESS3.1 On-chip memory architectures and management: Scratchpads, compiler controlled memories, etc.
ESS3.2 Embedded storage systems organization and management
ESS3.3 Memory and Storage hierarchies with emerging memory technologies
ESS3.3 Memory and Storage hierarchies with emerging memory technologies

ESS4. Near-Memory and In-Memory Computing

ESS4.1 Memory architecture and management for emerging memory technologies
ESS4.2 Data reorgainzation engines

ESS5 Time-Critical System Design

ESS5.1 Real-time analysis and tool flows
ESS5.2 WCET methods and tools for embedded hardware/software systems
ESS5.3 Mixed-Criticality system design
ESS5.4 HW-SW integration and system-level design for timing-critical systems
ESS5.5 Timing predictable resource sharing and management

SECURITY/PRIVACY

SEC1. Hardware Security I: Primitives, Architectures, Design, and Test

SEC1.1 Hardware security primitives for cryptography, key generation, and authentication
SEC1.2 Trusted IP and system-on-chip (SoC) design and manufacturingSEC1.3 Trusted IP and system-on-chip (SoC) design and manufacturing
SEC1.3 Emerging technologies (Nanoscale devices, 3D, etc.) and security
SEC1.4 Hardware security verification, validation and test

SEC2. Hardware Security II: Attack and Defense

SEC2.1 Hardware-enabled side-channel attacks and defenses
SEC2.2 Reverse engineering and hardware obfuscation
SEC2.3 Hardware supply chain protection and anti-counterfeiting

SEC3. Embedded and Cross-Layer Security

SEC3.1 Embedded software and system-level techniques for security
SEC3.2 Architectural support for software and embedded systems security
SEC3.3 Cyber-physical systems and IoT security
SEC3.4 Embedded security: metrics, models, verification and validation
SEC3.5 Machine learning for cyber defense
SEC3.6 Security vulnerabilities in artificial intelligence

Review and selection process

The DAC Technical Program Committee (TPC) determines the selection of research manuscripts to be included in the DAC program, as well as how they are integrated into technical sessions within the conference schedule. The Technical Program Committee is organized into several subcommittees, which focus on the various topic areas that are relevant to the conference. These are reasonably close, but not necessarily identical to the categories in the call for contributions. Manuscripts which are assigned by authors to unfitting categories may be reassigned by the program committee chair and subcommittee chairs to a subcommittee best able to review them.

DAC strives to ensure that there are no conflicts of interest (COI) between authors and reviewers so to provide a review process that is fair to all the authors. Submitters should report conflict of interests for all co-authors with members of the Technical Program Committee by the manuscript submission deadline, as discussed in the “Conflict of Interests” tab. The Technical Program Committee Chair may reassign manuscripts to different subcommittees to resolve conflicts of interest with Technical Program Committee members.

DAC will also compare each submission against a vast database to identify manuscripts which have significant similarity to previously published works. Submissions identified as plagiarized during this process will be rejected. Furthermore, the names of all the authors of the submission will be reported to IEEE, as well as the TPC Chair or the Editor-in-Chief of the venue where the duplicate was submitted. Further information on duplicate submissions is provided under the "Duplicate Submissions" tab at the top of this page.

Then DAC manuscripts undergo a double-blind review process; i.e., the identity of authors and reviewers is only known to the Technical Program Committee (TPC) Chair. Each subcommittee will select the best manuscripts submitted. The selectivity is influenced by the overall numbers of submissions, the capacity of the DAC schedule, and the number of manuscripts in each area.

The Technical Program Committee and its subcommittees will take into account the following aspects in selecting manuscripts:

Quality of the technical contribution (design, solution, methodology) described in the manuscript.
Originality of the concepts used and described. Advances over previous approaches should be reflected in the discussion of significant improvements in the results section. Comparisons with other approaches are also important to justify the advancement claimed in the submitted manuscript.
Significance of the results obtained, described by measurable quantitative criteria (runtime for tools, optimality of results, time for design process steps, simplification or automation of manual effort, etc.).
Degree of experimental evidence to support the claims of the manuscript. Results supported by evidence in industry-strength designs or widely accepted benchmarks with measurable criteria are highly desirable, if not essential.
A good discussion of limitations of the approach and concepts, and possible areas for future improvement.
The quality of manuscript writing, use of English, organization and clarity of presentation.
Once a manuscript has been accepted, the subcommittee organizes it into an appropriate technical session; sessions are then scheduled throughout the duration of the conference.

Copyright Info & Templates

One author of each accepted paper that is submitted to DAC for publication in the official conference proceedings is required by IEEE to sign a copyright form. Please note that paper copyright forms are no longer accepted and IEEE does not accept any addendum to their forms.

Copyright forms can be found here. These copyright samples are for your information only. Authors will be required to complete an electronic version of one of these forms through the IEEE submission system if their paper is accepted.
IEEE’s Publishing Policy can be found here and the Author Rights page can be found here.
Any issues/questions authors have regarding the copyright form or IEEE Policy may be addressed to IEEE.

Templates:

View suggested IEEE Proceedings Templates.
View previously accepted research manuscripts on the DAC Archive.

submissions are now closed

Abstract Deadline

Thursday, November 21, 2019
5:00PM (MST), (-7:00 GMT)

Manuscript Deadline

Wednesday, November 27, 2019
5:00PM (MST), (-7:00 GMT)

Contact Information

Jörg Henkel
Technical Program Chair
Email

Submission Site Questions