Join us at #DAC2026 to watch our fierce Engineering Track Poster Gladiators battle to see who will emerge as the winner of the DAC Gladiator Poster Award.
This new program recognizes the hard work and preparation the poster submitters have completed. Each Poster Gladiator finalist will be given 5-minutes in the DAC Pavilion on either the Monday, Tuesday, or Wednesday of DAC to present their submitted and approved poster presentation in a speed round. Presenters will be presenting in front of a panel of expert industry judges. In addition to the judges, the audience will also be partly responsible for determining the fate of each gladiator and deciding the winner.
Poster gladiators will be judged on the following criteria:
Engineering Tracks reviewer scores
Originality and creativity of the work being presented
Clarity and writing style
Impact of the gladiator's ideas and work
Battle MC - Brian Fuller, Arm
Judges
Ambar Sakar, 2026 Special Sessions Chair, Past Engineering Track Chair
Harry Foster, Siemens, DAC General Chair 2021
Mac McNamara, Adapt IP, DAC General Chair 2017
Rob Aitken, NAPMP, General Chair 2019
| Poster ID | Poster Title | Gladiators | Date | Time |
|---|---|---|---|---|
| 11 | AI-Enabled EDA Cloud Infrastructure and Design Optimization for Next-Generation Semiconductor Design | Jeroen Kusters, Nina Zhang and Mike Luk | Mon, July 27 | 17:00 - 17:07 |
| 69 | Flexible & Scalable Network Modeling for AI/HPC Network Verification | Sanghyeon Hwang and Minho Chu | Mon, July 27 | 17:07 - 17:14 |
| 159 | System-Level Modeling of Power Delivery Networks to Optimize Remote Sense Point Placement in Multi-Board Architectures | Santhanam P | Mon, July 27 | 17:14 - 17:21 |
| 226 | An AI-Enhanced Web-based Real-Time Analytics & Prediction Platform for ASIC Physical Design (PD) Flows | Subhash Uppala, Anoop Singh, Ayan Datta and Manjunath Nayak | Mon, July 27 | 17:21 - 17:28 |
| 388 | Cost-Based Partial Subgraph Matching for Circuit Pattern Recognition | Ashutosh Jadhav, Xin Zhao, Ehsan Degan and Vandana Mukherjee | Mon, July 27 | 17:28 - 17:35 |
| 412 | Configurable IP and Design Methodology for Edge AI | Sreepada V. Hegade | Mon, July 27 | 17:35 - 17:42 |
| 451 | Outsmarting State Space Complexity through Proven Reset Abstraction Stratergies | S R Pavitra, Sharika Shaju and Anshul Jain | Mon, July 27 | 17:42 - 17:49 |
| 453 | A Hybrid SRAM-DRAM Memory Architecture for Ultra-Low-Power Wakeup in SoCs | Prasad Basavaraj Dandra, Thejeswara Pocha Reddy, Tushar Vrind, Somraj Mani, Venkata Raju Indukuri, Krishnakant Patil and Amol Kumar Purushottam Jagtap | Mon, July 27 | 17:49 - 17:56 |
| 7 | BSPDN: A Power Delivery Architecture for 19.8% Core Power Reduction and 9.3C Thermal Mitigation in Next-Generation AI Processors | Dean Huang, Jim Yang and Jun Lu | Tue, July 28 | 17:00 - 17:07 |
| 131 | Predictive LV Compute Time for Multi-Resource Job Scheduling | Samichi Shrivastava, Meghana K M and Rajesh Karturi | Tue, July 28 | 17:00 - 17:07 |
| 53 | 3DEM-Driven STA for Cross-Die Timing Signoff in 3DIC Chiplets Heterogeneous Integration | Mingyang Liu, Yi Chen, Zhang Jie, Chunming Wang, Yue Heng, yu tian, Liangzhen Lai, Rodger Luo and zhenghao chu | Tue, July 28 | 17:14 - 17:21 |
| 133 | ML-Based Sigma AV–Aware Switch Cell Optimization | Sungsu Byun | Tue, July 28 | 17:21 - 17:28 |
| 66 | Efficient Electromagnetic Extraction of Superconducting Circuits Used with Quantum Computers and Rapid Single Flux Quantum Designs | Garth Sundberg | Tue, July 28 | 17:28 - 17:35 |
| 82 | A method to automate the conversion of .def file into .save.io one to speed up the BE digital flow in analog-on-top designs | Luca Pulvirenti, Mario Blangiforti, Luca Francesco Perroni and Michele Battista | Tue, July 28 | 17:35 - 17:42 |
| 105 | Multi Level EMFI Analysis Flow Using Electromagnetic Field Solver and Chip PDN Model | Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Makoto Nagata, Tianze Kan, Lang Lin and Norman Chang | Tue, July 28 | 17:42 - 17:49 |
| 337 | LLM-Aided Cell Clustering for Placement Optimization of DRAM Peripheral Circuits | Soyoon Choi, Chansol Hong, Jinyoung Lee and Hyojin Choi | Wed, July 29 | 17:49 - 17:56 |
| 319 | Faster Database Readiness for Physical Verification: With Calibre Design Enhancer PVR | Karishma Qureshi, Rakesh Katukuri Reddy, Anish Padhi, Fady Fouad and Arsen Asatryan | Wed, July 29 | 17:00 - 17:07 |
| 218 | A Unified Silicon-Correlated Characterization Flow for High-PPA Standard Cell Libraries at Advance Nodes | Pramod Gayakwad, santhosh kamatam, Khushboo Rathore and Rajesh Kotha | Wed, July 29 | 17:00 - 17:07 |
| 305 | Sigma Profiling: Profiling Solution for Power Integrity Signoff | Girish Deshpande, Anusha Vemuri, Vishal Malik, Emmanuel Chao, Santosh Santosh, Chidambaram Rakkappan, Ayush Sood and Tapas Govindraju | Wed, July 29 | 17:14 - 17:21 |
| 425 | Agile Silicon: A GitOps-Based PD Orchestration Framework Enabling <10-Person PD Team to Deliver CPO Tapeouts | Ruosi Moira Feng, Aadvivian Singh, Jonathan Elmhurst and Rishi Anand | Wed, July 29 | 17:21 - 17:28 |
| 353 | Accurate Full-Custom Thermal and EM Analysis for Advanced Nodes | David Newmark | Wed, July 29 | 17:28 - 17:35 |