2026 TechTalks Speakers

As design complexity accelerates, time-to-market pressures intensify, and the specialized EDA workforce declines, the traditional approach of using EDA tools in isolation and then iterating on the design is reaching its limit. Specifically, this shrinking workforce cannot handle iterating on multiple design options while ensuring designs are verified and DRC-clean in ever-shorter timeframes.

This presentation outlines how EDA AI agents can work individually and collaboratively—using advanced reasoning, multi-tool integration, and data analysis—to enable a fully autonomous end-to-end EDA workflow by leveraging direct API integrations, MCP, and Agent skills.

We demonstrate this across the complete EDA workflow: (a) C-to-RTL-to-GDS flows generate RTL and deploy PPA optimization agents; (b) custom IC and analog/mixed-signal workflows leverage autonomous setup builders and intelligent debugging with data flywheel approaches for continuous agent refinement; (c) physical verification benefits from intelligent DRC remediation, run optimization, and SVRF deck generation. Each domain showcases how agentic AI eliminates manual intervention while improving outcomes, both in-tool and across multiple tools.

To tie everything together, we then showcase how Siemens EDA is solving these challenges with the newly launched Fuse EDA AI System and the Fuse Agent, which are purpose-built to enable AI-powered automations in EDA. Lastly, we highlight that completing this transformation represents a new design philosophy: one in which engineers and AI agents collaborate as co-designers, each amplifying the other’s strengths across the full EDA workflow.

Design verification remains one of the most time-intensive and expertise-dependent stages of chip development, routinely consuming over 70% of total project effort. As AI agents mature from research prototypes into production tools, the DV community faces a pivotal question: are these systems actually ready for real tapeouts?

This talk presents lessons learned from deploying AI agents across production DV environments from block-level designs to full-chip SoC verification. We describe an agentic architecture that autonomously produces root-cause analyses and suggested fixes in under 15 minutes while operating under the realities of security, efficiency, and integration with existing flows..

Across a diverse set of production issues, we demonstrate a 70% end-to-end success rate on first-pass debug. We discuss what makes agents succeed and fail, and share how an AI-native EDA toolstack plus advanced layers for planning and institutional knowledge are foundational to achieving this level of reliability. This includes rethinking how agents access waveforms, query design databases, and interact with simulation infrastructure at scale. 

We argue that the bottleneck to an AI-native EDA stack is no longer model capability — it is infrastructure, integration, and trust. 

Artificial intelligence is now deeply embedded in the semiconductor design conversation, but separating real engineering impact from aspirational hype remains a challenge for both technical and business leaders. This TechTalk provides a clear, grounded view of where Agentic AI is actually delivering measurable value in chip design workflows today, and where expectations still exceed practical reality.

The talk will examine concrete use cases across the design lifecycle, including architectural exploration, RTL quality analysis, verification acceleration, physical design optimization, and design closure. Rather than focusing on specific tools or products, the presentation will emphasize underlying techniques, deployment patterns, and organizational lessons learned from real-world adoption. Key questions addressed include: What types of design problems are well-suited for modern agentic AI approaches? Where do data availability and model generalization break down? How do teams integrate AI into existing EDA flows without disrupting proven methodologies?

The session will also explore the implications for engineering productivity, time-to-market, and design risk, helping business stakeholders understand where Agentic AI investments pay off, and where caution is warranted. By bridging technical depth with strategic insight, this TechTalk aims to equip DAC attendees with a realistic framework for evaluating and deploying AI in semiconductor design. This presentation aligns with DAC’s AI, Design, and EDA pillars and is intended for design engineers, CAD managers, and technology decision-makers seeking practical guidance rather than marketing narratives.