2026 SkyTalk Speakers

A new era is emerging where AI supercomputing and EDA come together to redefine what is possible in chip and system design. Accelerated computing, foundation models, and intelligent design flows are transforming every stage of the journey, from architecture and verification to deployment in complex, secure systems. As AI, Design, EDA, Security, and Systems converge, design cycles can shrink, chiplet-based and future quantum-ready platforms can become practical, and human creativity can be amplified. This keynote explores how collaborating with AI at scale can unlock breakthrough performance, faster innovation, and a new generation of chips and systems that power the world’s most ambitious ideas.

There is a rapid transition occurring in the world today - companies are driving from an internet economy to an AI economy. AI and HPC performance demands are increasing at a rapid clip and newer innovations in Si, Package and System designs are needed to meet the increased demand and to fully realize the power of AI. The demand for performance surged by nearly 10x over a two-year period (2021-2022), rapidly outpacing Moore’s Law, which traditionally doubles transistor counts roughly every 18 months. Performance and cost at the system level are key vectors that will require optimization across the entire stack to meet these demands. Heterogeneous integration of chiplets in an advanced package is essential to pave the way for sustainable scaling in the AI era.

In this presentation, I will cover our approach to chiplet design, advanced packaging, and interconnect technologies to ensure a fully optimized solution for AI needs. Intel as a system foundry is driving System Technology Co-Optimization (STCO) across the entire stack to achieve these goals.  Intel has played a pioneering role in advancing chiplet-based architecture through its leadership in interconnect standardization, packaging innovation, and disaggregated design strategies and I will address key aspects in this talk.

In this talk, we examine how the semiconductor industry handled key inflections in the past decade and share perspectives on the path to enable 7Å in the upcoming years anticipating the next key inflection point. 

The rapid growth of artificial intelligence (AI) applications is driving unprecedented demand for high‑performance, energy‑efficient AI accelerators, placing new and complex demands on Electronic Design Automation (EDA) flows. Scaling these designs from chips to full systems introduces challenges that traditional EDA methodologies were not built to handle.

With increasing accelerator size and complexity, traditional EDA tools and methodologies face challenges spanning advanced process nodes, large‑scale parallelism, and system‑level performance and data movement. These issues increasingly emerge at the boundaries between compute, memory, interconnect, and software behavior, where system‑level interactions has significant impact on design outcomes. In addition, the speaker will discuss the evolving landscape of EDA tools, highlighting the augmentation of conventional methodologies with AI-driven approaches to better address the increasing intricacy and verification demands in hardware design. Emerging trends such as hardware‑software co‑design, faster iteration through prototyping and comprehensive design‑space exploration are discussed as key approaches to addressing these challenges.

Attendees will leave with practical insights into current limitations of EDA at AI scale, emerging solutions being deployed in production environments, and the implications for next‑generation accelerator and system design – from silicon architects to EDA practitioners working across the full chips‑to‑systems stack.