Celebrate 60 Years with DAC this July
For 60 years, DAC has been the premier destination for the entire ecosystem devoted to the design and design automation of electronic circuits and systems. DAC offers the electronic design ecosystem outstanding education, training, exhibits and networking opportunities for a worldwide community of chip & system designers, researchers, academics, executives, and electronic design tool vendors to engage and reconnect. Don't miss your chance to attend and see DAC in action with top presentations from:
Cadence Design Systems
University of Bologna
Joseph Sawicki is a leading expert in IC nanometer design and manufacturing challenges. Formerly responsible for Mentor's industry-leading design-to-silicon products, including the Calibre physical verification and DFM platform and Mentor's Tessent design-for-test product line, Sawicki now oversees all business units in the Siemens EDA IC segment. Sawicki joined Mentor Graphics in 1990 and has held previous positions in applications engineering, sales, marketing, and management. He holds a BSEE from the University of Rochester, an MBA from Northeastern University's High Technology Program, and has completed the Harvard Business School Advanced Management Program.
Prith Banerjee is the Chief Technology Officer of Ansys where he is responsible for leading the evolution of Ansys' Technology strategy and champion the company's next phase of innovation and growth Formerly, he was Executive Vice President, Chief Technology Officer of Schneider Electric. Previously, Prith was Managing Director of Global Technology Research and Development at Accenture. Formerly, he was Chief Technology Officer and Executive Vice President of ABB. Earlier, he was Senior Vice President of Research at HP and Director of HP Labs. Formerly, Prith was Dean of the College of Engineering at the University of Illinois at Chicago. Formerly, he was the Walter P. Murphy Professor and Chairman of Electrical and Computer Engineering at Northwestern University. Prior to that, Prith was Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. In 2000, he founded AccelChip, a developer of products for electronic design automation, which was acquired by Xilinx Inc. in 2006. During 2005-2011, he was Founder, Chairman and Chief Scientist of BINACHIP Inc., a developer of products in electronic design automation. FastCompany listed Prith in their 100 top business leaders in 2009. He is a Fellow of the AAAS, ACM and IEEE, and a recipient of the 1996 ASEE Terman Award, the 2001 Taylor Booth Award from IEEE, and the 1987 NSF Presidential Young Investigator Award. Prith earned a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.
Lip-Bu Tan has served as Executive Chair of the Board of Directors of Cadence since December 2021 and has been a member of the Cadence Board of Directors since February 2004. He served as CEO of the company from 2009 to 2021 and as President from 2009 to 2017. He also serves as chairman of Walden International, the venture capital firm he founded in 1987, and is a founding managing partner of Walden Catalyst Ventures. Prior to joining Cadence, Mr. Tan was Vice President at Chappell & Co. and held management positions at EDS Nuclear and ECHO Energy. Mr. Tan is a member of The Business Council and serves on the boards of directors of Intel Corporation, Schneider Electric SE, Credo Technology Group Holding Ltd., and Green Hills Software. He also serves on the Board of Trustees and the School of Engineering Dean's Council at Carnegie Mellon University and on the University of California, Berkeley's Engineering Advisory Board. Mr. Tan received the Semiconductor Industry Association (SIA)'s 2022 Robert N. Noyce Award and the Global Semiconductor Alliance (GSA)'s 2016 Morris Chang Exemplary Leadership Award. Mr. Tan received a BS from Nanyang University in Singapore, an MS in nuclear engineering from the Massachusetts Institute of Technology, and an MBA from the University of San Francisco.
Cecilia Metra is a Professor and the Deputy President of the School of Engineering at the University of Bologna, Italy, where she has worked since 1991, and from which she received the Laurea Degree in Electronic Engineering and the PhD in electronic engineering and computer science. In 2002, she was visiting faculty consultant for Intel Corporation. She is part of the Italian National Research Center on High Performance Computing, Big Data and Quantum Computing, and of the Italian Research Project on Security and Rights In the CyberSpace. She is 2022-2023 IEEE Director, Division V, and she was the 2019 President of the IEEE Computer Society. She is Co-Chair of the "IEEE Metaverse" Project of the IEEE Future Directions, and a member of several IEEE Committees, including the IEEE Conferences and the IEEE Award Committees. She was a member of the Board of Governors of the IEEE Computer Society and the IEEE CEDA. She was Editor-in-Chief of the IEEE Transactions on Emerging Topics in Computing, and Associate Editor-in-Chief of the IEEE Transactions on Computers. She contributed to numerous IEEE international conferences/symposia/workshops as General/Program Chair, Technical Program Committee member, and Keynote/Invited Speaker.
Alberto L. Sangiovanni-Vincentelli
Dr. Walden Rhines
Alberto Sangiovanni Vincentelli is the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California at Berkeley. In 1980-1981, he was a Visiting Scientist at the Mathematical Sciences Department of the IBM T.J. Watson Research Center. In 1987, he was Visiting Professor at MIT. He is an author of over 800 papers, 17 books and 2 patents in the area of design tools and methodologies, large scale systems, embedded systems, hybrid systems and innovation. He was a co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation and the founder and Scientific Director of the PARADES Research Center in Rome.
Heike Riel is IBM Fellow, Head of Science & Technology and Lead of IBM Research Quantum Europe at IBM Research. She is responsible for leading the research agenda of the Science & Technology department aiming to create scientific and technological breakthroughs in Quantum Computing, Physics of Artificial Intelligence, Nanoscience and Nanotechnology, Precision Diagnostics and Smart System Integration. She is a distinguished expert in nanotechnology and nanosciences and focuses her research on advancing the frontiers of information technology through the physical sciences. She contributed to advancements in the science and technology of nanoscale electronics, in particular the exploration and development of semiconducting nanowires and nanostructures for applications in future electronic and optoelectronic devices, in molecular electronics for future nanoscale switches and memory applications, and organic light-emitting diodes for display applications. Her current research interests include new materials and device concepts for future nanoelectronics for applications in quantum computing and neuromorphic computing. She also serves as the Deputy Director of the new Swiss National Competence Center for Research on Silicon Spin Qubits.
Mark Horowitz is the Yahoo! Founders Professor at Stanford University and was chair of the Electrical Engineering Department from 2008 to 2012. He received his BS and MS in Electrical Engineering from MIT in 1978, and his PhD from Stanford in 1984. Dr. Horowitz has received many awards for his work and has broad research interests. He has worked on many processor designs, from early RISC chips and in 1990 he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology. His work at both Rambus and Stanford drove high-speed link designs for many decades. In the 2000s he started a collaboration with Marc Levoy in computational photography which led to light-field photography and microscopy. His current research includes updating both analog and digital design methods, agile hardware design, and applying engineering to biology. He remains interested in learning new things, and building interdisciplinary teams.
Dr. Dev Shenoy
Department of Defense
Cadence Design Systems
Dr. Dev Shenoy joined the Office of the Under Secretary of Defense for Research and Engineering, OUSD(R&E), as the Principal Director for Microelectronics in July 2021. In this role, Dr. Shenoy is responsible for leading the Department of Defense's research and engineering efforts in Microelectronics. Prior to joining OUSD(R&E), Dr. Shenoy served as the Director of Microelectronics Innovation and as Director of Advanced Technologies at the University of Southern California's Information Sciences Institute. Prior to joining USC/ISI, Dr. Shenoy served as Chief Engineer in the Advanced Manufacturing Office at the Department of Energy (DOE) HQ. In that role, he co-authored DOE's 2015 QTR (Quadrennial Technology Review) that served as a blueprint for DOE's energy technology investments. Among other initiatives, Dr. Shenoy proposed and led a "Big Idea" for U.S. national security and economic competitiveness within the Office of EERE (Energy Efficiency and Renewable Energy) on "Beyond Moore Computing" with participation from eight DOE National Labs. Prior to joining DOE, Dr. Shenoy served as a Senior Advisor at the Manufacturing and Industrial Base Policy (MIBP) Office within the Office of the Secretary of Defense (OSD) as a detailee from the Army Night Vision and Sensors Directorate (NVESD) at Fort Belvoir. In that role, he co-led a Telecom initiative with the White House Office of Science and Technology Policy (OSTP) to explore U.S. opportunities in Optical networks.
Dr. Paul Cunningham has served as Senior Vice President and General Manager of the System Verification Group (SVG) since March 2021, running the division since 2018. His responsibilities include logic simulation, emulation, prototyping, formal verification, Verification IP, and functional debug. Prior to this role, Cunningham was responsible for Cadence's frontend digital design tools including logic synthesis and design-for-test. Dr. Cunningham joined Cadence in 2011 via the acquisition of Azuro, a startup developing concurrent physical optimization and useful skew clock tree synthesis technologies, where he was a co-founder and CEO. Dr. Cunningham holds a MS and a PhD in Computer Science from the University of Cambridge in the UK.
Pioneer of artificial intelligence processors, Jean-Philippe (J.P.) Fricker is the creator of the biggest and fastest computer chip in the world, the Cerebras Wafer-Scale Engine. Co-founder and Chief System Architect of California company Cerebras Systems (2016), he specializes in AI systems based on neural networks. Through his company, he co-developed the largest chip ever (the size of a dinner plate), where all 850,000 cores run on the same processor. Prior to co-founding Cerebras, J.P. was Senior Hardware Architect at rack-scale flash array startup DSSD and Lead System Architect at SeaMicro where he designed three generations of fabric-based computer systems. Earlier in his career, J.P. was Director of Hardware Engineering at Alcatel-Lucent and Director of Hardware Engineering at Riverstone Networks. J.P. is a member of the Swiss Academy of Engineering Sciences SATW. He holds an MS in Electrical Engineering from École Polytechnique Fédérale de Lausanne, Switzerland, and has authored 40 patents.
Meta Reality Labs
Young Innovator, Ham Radio Operator (KJ7NLL)
Software Competence Center
Majid Ahadi Dolatsara
Edith Beigné is the Research Director of AR/VR Silicon at Meta Reality Labs where she leads research projects driving the future of AR devices. Her main research interests are low power digital and mixed-signal circuits and design with emerging technologies. Over the past 20 years, she has been focusing her research on low power and adaptive circuit techniques, exploiting new design techniques and advanced technology nodes for different applications ranging from high performance multi-processors to ultra-low power SoC, and, more recently, AR/VR applications. She is the Executive vice chair of ISSCC 2024, was the technical chair of ISSCC 2022 and part of ISSCC TPC since 2014, part of VLSI symposium TPC between 2015 and 2020. Distinguished Lecturer for the SSCS in 2016/2017, Women-in-Circuits Committee chair and JSSC Associate Editor since 2018. She visited Stanford University in 2018 to research on emerging technologies and new architectures.
Robert Wille is Full and Distinguished Professor at the Technical University of Munich, Germany, and Chief Scientific Officer at the Software Competence Center Hagenberg GmbH, Austria (a technology transfer company with more than 100 employees). For more than 15 years, he is working on topics in the domain of quantum computing and successfully established design automation concepts in this domain. The impact of his work is reflected by numerous awards such as Best Paper Awards, e.g., at TCAD and ICCAD, a DAC Under-40 Innovator Award, a Google Research Award, etc., collaborations with industrial partners in this domain, as well as his involvement in prestigious projects and initiatives, e.g., within the scheme of an ERC Consolidator Grant or the comprehensive quantum computing initiative of the Munich Quantum Valley.
Majid Ahadi Dolatsara received the B.Sc. degree in electrical engineering from K. N. Toosi University of Technology, Tehran, Iran, in 2013, the M.Sc. degree in electrical engineering from Colorado State University, Fort Collins, CO, USA, in 2016, and the Ph.D. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2021. He has won the Richard B. Schulz best paper award in transactions on electromagnetic compatibility in 2022.
He is currently employed by Keysight Technologies, Calabasas, CA, USA, as a research and development software engineer, working on electronic design automation software. His research interests include development of numerical and machine learning algorithms for high performance simulation in the area of signal and power integrity.
Zeke Wheeler is twelve years-old and demonstrated an early interest in engineering. In April he received the Best Presentation Award in the Multiphysics In-Design Analysis Track at CadenceLIVE 2023. Since 2020 he has been working to contact the International Space Station, using circuit boards and antennas designed in Microwave Office, and a satellite tracker made from Legos. He looks forward to sharing his project with the DAC community.
Erik Berg is a Principal Engineer at Microsoft and an innovative leader in the field of SoC verification.
With a career that has been guided by the ambition to maximize the impact of everyone on his team, Erik brings a unique perspective to his work. He is driven by the challenge of scaling verification teams and reducing risk through methodology, tooling, and automation initiatives. As part of Erik's passion for pushing the boundaries of hardware development, he leads Microsoft's Steering Group for the application of machine learning and artificial intelligence in this domain.
One of Erik's notable contributions to the field is the invention of the Debug Decision Tree (DDT) tool. Recognizing the critical importance of debug efficiency, he developed DDT to enhance debug knowledge sharing and automation and collaborated with Synopsys to launch DDT to the market in 2023.
Before joining Microsoft, Erik spent 19 years at Intel, holding verification roles covering IP, SOC, formal, power, and performance. His extensive experience across different domains has provided him with a comprehensive understanding of the complexities involved in creating cutting-edge hardware solutions.
Beyond his professional achievements, Erik holds a PhD from the University of Michigan, specializing in nanofabrication and single electron transistors. His academic background reflects his commitment to staying at the forefront of technological advancements.