2022 TechTalk Speakers
View the Entire 2022 Conference Program
Is Curvy Design an Opportunity or a Dream?
Monday, July 11, 2022
The semiconductor manufacturing community is ready for the first time in 40 years to enable a wholesale change in what future chips could look like by manufacturing curvilinear features. But most of the chip design community doesn’t know that and this talk is about bridging that awareness from manufacturing to the design community. The entire chip design infrastructure is based on the Manhattan assumption. In my previous life in EDA, I had something to do with that, so I know this very well. I also know this is not going to change any time soon. At the same time, though, is there any doubt that a curvilinear “curvy” chip, if magically made possible, would be smaller, faster, and use less power? Of course not. The shortest distance between two points is a straight line. And the least resistive path is a smoothly curved path, not a series of 90 degree turns. Another thing we know from my current life in software for semiconductor manufacturing: a target shape that is easier to manufacture is more reliably manufacturable. And 90-degree turns are not manufacturable, but smooth curvilinear turns are. Curvy designs would yield better, decrease chip size and perform more consistently. There’s an opportunity to take advantage of what semiconductor manufacturing has enabled for the first time in 40 years. In this talk, I’ll provide a baseline education of how photomasks and wafers are manufactured then summarize the changes in semiconductor manufacturing that enable curvy designs. My goal is to explain why manufacturing is no longer a barrier to curvy design and spark the imagination of the EDA and design community.
Open Architectures to Accelerate Industry Growth
Tuesday, July 12, 2022
There is an exponential growth in demand for workload specific compute in artificial intelligence (both training and inference), network and storage acceleration, 5G/6G edge servers, media acceleration, high performance compute (ex. Vector processing), graphics, and gaming. The industry is facing many architectural challenges to improve cost, performance, power, security, etc. to meet this demand. The solution will require a broad alignment around standardized open architectures from the ISA to the SoC level, alignment of the IP supplier ecosystem, cooperation in standards, new EDA tools, and support from foundries and packaging suppliers.
These open architectures will need to support the established and growing SW ecosystem around x86 while seamlessly blending in RISC-V as the new open ISAs at the center of domain specific computation. RISC-V as a new open architecture will need industry cooperation to mature the ISA, the SoC silicon architecture, the platform architecture, and the open-source software stack.
These open architectures must embrace disaggregation. The new disaggregated architectures will need new packaging technologies to be co-optimized with interconnect technologies with full support from Foundries and the IP Ecosystem. New EDA tools will be needed to optimize the overall silicon partitioning and accelerate the development cycles of each partition.
This talk will highlight some of the recent progress in the industry, and a call to collaborate on enabling and supporting these new architectures.
About: Bob Brennan is Vice President of Customer Solutions Engineering for Intel Foundry Services at Intel Corporation. He is responsible for leading the delivery of end-to-end design solutions to help IFS customers use Intel’s portfolio of unique IPs and design technology in their product designs. This responsibility covers the entire design life cycle for customers, from customer design architecture to the strategic selection of Intel IP to platform enablement, as well as design services support for SoC integration including validation and debug support. Bob also has the honor of serving as a board member for RISC-V International. In his previous role, Bob served as Vice President of Emerging Memory & System at Micron, where he managed product, design, and engineering teams to accelerate the delivery of new designs on new technologies. Before that, Bob served as Senior Vice President of Memory Solutions Lab at Samsung, where he established an Enterprise SSD product line, delivered Samsung’s first revenue software product while continuing an active role in architecture development. Prior to these roles, Bob spent 22 years at Intel serving in various senior technical positions, including Server Architecture, Laptop Architecture, Mobile SoC Architecture, and CPU Core Design, Verification and Architecture.
Co-Design for Edge Intelligence: Perception, Control, Computing
Wednesday, July 13
Autonomous vehicles combine machine learning-based perception with planning and control. Co-design introduces the opportunity for new types of optimizations for perception that range across accuracy, execution time, and power consumption. The requirements on embedded computer vision for autonomy include accuracy, latency, and power consumption. These requirements interact---for example, long latencies can interfere with control performance. This talk will explore the use of co-design to create highly capable and efficient autonomous systems.
About: Marilyn C. Wolf has enabled a new generation of researchers to conceptualize, build, and validate modern embedded computing systems through influential textbooks, high-impact conferences, and mentoring graduate students. These computers embedded within physical objects power our world in transportation, healthcare, and many other disciplines. Wolf wrote one of the first textbooks in the field, Computers as Components: Principles of Embedded Computing System Design, as well as High-Performance Embedded Computing: Applications in Cyber-Physical Systems and Mobile Computing, which is geared specifically to graduate courses. She has helped to create many of the technical meetings and technical publications in the field, including Embedded Systems Week and the journal Design Automation for Embedded Systems, providing essential forums for graduate students.
An IEEE Fellow, Wolf is the Elmer E. Koch Professor of Engineering and Director of the School of Computing at the University of Nebraska–Lincoln, Lincoln, NE, USA.