2023 Keynote Speakers

Corsi e Ricorsi: Here We Go Again

Monday, July 10

In 2003, I argued that semiconductor and system design, and design automation, have evolved by way of a repeating pattern of intuitive approaches, great insights and rigorous, if conservative, methodologies that I called “Corsi e Ricorsi”, using the principles of Giambattista Vico, history philosopher of the XVI Century. Over the course of six decades, this phenomenon fueled an evolution in technologies and computational software that gradually freed silicon and system designers from the shackles of choice, empowering them to overcome 18 orders of magnitude of design complexity to date, never failing to bring the possibility horizon closer.

I will present the evolution of EDA as an effective and powerful early example of Artificial Intelligence, in its broadest sense as “the theory and development of computer systems able to perform tasks that normally require human intelligence”, separate the hype from reality, comment on the present frenzy around machine learning applied to EDA, and reassure our community that design automation engineering is, more than ever, one of the world’s most natural intelligence rich professions. Finally, I will discuss the challenges posed to EDA by the development of 3D integrated circuits and put them in the context of the evolution of packaging methods over the past 40 years.

ABOUT: Alberto Sangiovanni Vincentelli is the Edgar L. and Harold H. Buttner Chair of Electrical Engineering and Computer Sciences at the University of California at Berkeley. In 1980-1981, he was a Visiting Scientist at the Mathematical Sciences Department of the IBM T.J. Watson Research Center. In 1987, he was Visiting Professor at MIT. He is an author of over 800 papers, 17 books and 2 patents in the area of design tools and methodologies, large scale systems, embedded systems, hybrid systems and innovation. He was a co-founder of Cadence and Synopsys, the two leading companies in the area of Electronic Design Automation and the founder and Scientific Director of the PARADES Research Center in Rome

Quantum Computing Roadmap

Tuesday, July 11

Despite the continued advances of digital computing including accelerators for artificial intelligence, there are still many important and relevant mathematical problems that are intractable for classical computers. Quantum Computers are a radically different approach and open a new trajectory to evolve computation and enable solving difficult and complex problems. In the past years significant progress has been made toward understanding the scope of quantum computing, pushing its hardware and software technology, developing applications, and advancing error mitigation/correction protocols. An entire new computing system is built from the bottom up. Advancing the state-of-the-art as quickly as possible requires pursuing in parallel improvements in three key metrics - scale, quality, and speed of quantum systems, as well as simultaneously providing advanced capabilities to exploit the performance and make them easy to use. Integrating new technologies such as advanced packaging, high-density control signal delivery, developing advanced qubit control electronics have already enabled scaling of superconducting quantum processors to 433-qubits. Combined with increases in quality and speed this has driven significant improvements in the performance of quantum computers. Moreover, the computational capabilities of today’s quantum hardware can be extended by tight integration of quantum and classical resources using techniques like circuit knitting to accelerate the path towards quantum advantage. Developing approaches to connect individual quantum processors in various ways with classical as well as quantum communication links enables a modular approach to further scale quantum systems.

ABOUT: Heike Riel is IBM Fellow, Head of Science & Technology and Lead of IBM Research Quantum Europe at IBM Research. She is responsible for leading the research agenda of the Science & Technology department aiming to create scientific and technological breakthroughs in Quantum Computing, Physics of Artificial Intelligence, Nanoscience and Nanotechnology, Precision Diagnostics and Smart System Integration. She is a distinguished expert in nanotechnology and nanosciences and focuses her research on advancing the frontiers of information technology through the physical sciences. She contributed to advancements in the science and technology of nanoscale electronics, in particular the exploration and development of semiconducting nanowires and nanostructures for applications in future electronic and optoelectronic devices, in molecular electronics for future nanoscale switches and memory applications, and organic light-emitting diodes for display applications. Her current research interests include new materials and device concepts for future nanoelectronics for applications in quantum computing and neuromorphic computing. She also serves as the Deputy Director of the new Swiss National Competence Center for Research on Silicon Spin Qubits.

Taking AI to the Next Level

Wednesday, July 12, 2023

With forty years of involvement in product development of AI-related products, Dr. Rhines brings perspective to the emerging capabilities that will take AI to the next level of commercial reality. One of the most important enablers is the ability to protect data privacy and ownership while making the data available for intelligent queries.
Rhines will address these and other issues that will drive the next wave in the AI revolution.

ABOUT: Walden C. (Wally) Rhines is President and CEO of Cornami, Inc., a fabless semiconductor and software company focused on fully homomorphic encryption. He was previously CEO of Mentor Graphics for 25 years and Chairman of the Board for 17 years. During his tenure at Mentor, revenue nearly quadrupled and market value of the company increased 10X.

Prior to joining Mentor Graphics, Dr. Rhines was Executive Vice President, Semiconductor Group, responsible for TI’s worldwide semiconductor business.

Dr. Rhines has served on the boards of Cirrus Logic, QORVO, TriQuint Semiconductor, Global Logic, PTK Corp., Silvaco, Pallidus and as Chairman of the Electronic Design Automation Consortium (five two-year terms). He is a Lifetime Fellow of the IEEE.

Dr. Rhines holds a Bachelor of Science degree in engineering from the University of Michigan, a Master of Science and PhD in materials science and engineering from Stanford University, an MBA from Southern Methodist University and Honorary Doctor of Technology degrees from the University of Florida and Nottingham Trent University.

In 2021, the Global Semiconductor Alliance honored Dr. Rhines, with its prestigious Dr. Morris Chang Exemplary Leadership Award.

Life Post Moore’s Law: The New CAD Frontier

Thursday, July 13

For over 50 years, information technology has relied upon Moore’s Law: providing, for the same cost, 2x the number of logic transistors that were possible a few years prior. For much of that time, the smaller devices also provided dramatic energy and performance improvement through Dennard Scaling, but that scaling ended over a decade ago. While technology scaling continues, per transistor cost is no longer scaling in the advanced nodes. In this post Moore’s Law reality, further price/performance improvement follows only from improving the efficiency of applications using innovative hardware and software techniques. Unfortunately, this need for innovative system solutions runs smack into the enormous complexity of designing and debugging contemporary VLSI based hardware/software platforms; a task so large it has caused the industry to consolidate, moving it away from innovation. To overcome this challenge, we need to develop a new set of CAD tools to enable small groups of application experts to selectively extend the performance of those successful platforms. Like the ASIC revolution in the 1980s, the goal of these tools is to enable a new set of designers, then board level logic designers, now application experts, to leverage the power of customized silicon solutions. Like then, these tools won’t initially be useful for current chip designers, but over time will underly all designs. In the 1980s to provide access to logic designers, the key technologies were logic synthesis, simulation, and placement/routing of their designs to gate arrays and std cells. Today, the key is to realize you are creating an “app” for an existing platform, and not creating the system solution from scratch (which is both too expensive and error prone), and to leverage the fact that modern “chips” are made of many chiplets. The new set of tools must provide a design window familiar to application developers, with similar descriptive, performance tuning, and debug capabilities. These new tools will be tied to highly capable platforms that are used as the foundation, like the appStore model for mobile phones. This talk will try to convince you this might be possible, and where innovative tools are needed.

ABOUT: Mark Horowitz is the Yahoo! Founders Professor at Stanford University and was chair of the Electrical Engineering Department from 2008 to 2012. He received his BS and MS in Electrical Engineering from MIT in 1978, and his PhD from Stanford in 1984. Dr. Horowitz has received many awards for his work and has broad research interests. He has worked on many processor designs, from early RISC chips and in 1990 he took leave from Stanford to help start Rambus Inc, a company designing high-bandwidth memory interface technology. His work at both Rambus and Stanford drove high-speed link designs for many decades. In the 2000s he started a collaboration with Marc Levoy in computational photography which led to light-field photography and microscopy. His current research includes updating both analog and digital design methods, agile hardware design, and applying engineering to biology. He remains interested in learning new things, and building interdisciplinary teams.