2023 SKYTalk Speakers
Microelectronics Security: A Growing National Imperative
Monday, July 10, 2023 | 1:00 pm - 1:45 pm
The microelectronics industry continues to play a fundamental role in our nation's economic and national security, and technological standing. The recent CHIPS Act and ongoing Department of Defense initiatives such as the Rapid Assured Microelectronics Prototypes (RAMP) program, underscore the government's commitment to accelerating the nation's rapid pace of microelectronics innovation and enable U.S. development of the very best in circuit design, manufacturing, and packaging. But how are we ensuring security across the microelectronics supply chain?
Dr. Devanand Shenoy will provide insights into how a number of DoD and commercial initiatives and investments are strengthening our microelectronics security posture across the development and deployment of leading-edge microelectronics technologies. Learn more about how these programs present opportunities for the Design Automation Conference (DAC) community to participate in the strengthening of our microelectronics cybersecurity readiness.
ABOUT: Dr. Dev Shenoy joined the Office of the Under Secretary of Defense for Research and Engineering, OUSD(R&E), as the Principal Director for Microelectronics in July 2021. In this role, Dr. Shenoy is responsible for leading the Department of Defense’s research and engineering efforts in Microelectronics. Prior to joining OUSD(R&E), Dr. Shenoy served as the Director of Microelectronics Innovation and as Director of Advanced Technologies at the University of Southern California’s Information Sciences Institute. Prior to joining USC/ISI, Dr. Shenoy served as Chief Engineer in the Advanced Manufacturing Office at the Department of Energy (DOE) HQ. In that role, he co-authored DOE’s 2015 QTR (Quadrennial Technology Review) that served as a blueprint for DOE’s energy technology investments. Among other initiatives, Dr. Shenoy proposed and led a “Big Idea” for U.S. national security and economic competitiveness within the Office of EERE (Energy Efficiency and Renewable Energy) on “Beyond Moore Computing” with participation from eight DOE National Labs. Prior to joining DOE, Dr. Shenoy served as a Senior Advisor at the Manufacturing and Industrial Base Policy (MIBP) Office within the Office of the Secretary of Defense (OSD) as a detailee from the Army Night Vision and Sensors Directorate (NVESD) at Fort Belvoir. In that role, he co-led a Telecom initiative with the White House Office of Science and Technology Policy (OSTP) to explore U.S. opportunities in Optical networks.
Entering a New Era with EDA 2.0 and AI-Driven Electronic System Design
Tuesday, July 11, 2023 | 1:00 pm - 1:45 pm
At Cadence, we see a great opportunity for our industry to enter a new era of EDA 2.0, defined by AI-driven platforms that optimize horizontally across multiple runs of many tools throughout an entire system design program. Learn how EDA 2.0 is bringing all design and verification data together under a unified data platform—RTL, layouts, constraints, waveforms, coverage, reports, log files, state graphs, AI models, and metadata with our new Cadence Joint Enterprise Data and AI (JedAI) Platform.
ABOUT: Dr. Paul Cunningham has served as Senior Vice President and General Manager of the System Verification Group (SVG) since March 2021, running the division since 2018. His responsibilities include logic simulation, emulation, prototyping, formal verification, Verification IP, and functional debug. Prior to this role, Cunningham was responsible for Cadence's frontend digital design tools including logic synthesis and design-for-test. Dr. Cunningham joined Cadence in 2011 via the acquisition of Azuro, a startup developing concurrent physical optimization and useful skew clock tree synthesis technologies, where he was a co-founder and CEO. Dr. Cunningham holds a MS and a PhD in Computer Science from the University of Cambridge in the UK.
The Cerebras CS-2: Designing an AI Accelerator Around the World's Largest 2.6 Tillion Transistor Chip
Wednesday, July 12, 2023 | 1:00 pm - 1:45 pm
Today’s exponential growth of neural networks is creating a demand for compute infrastructure that can’t keep up with the traditional performance improvements gained through enhancements of semiconductors technology nodes. A co-designed approach is needed to keep up with the demand. We explore how increasing chip dimensions and resulting power and cooling densities are some of the enabling vectors of such co-design.
ABOUT: Pioneer of artificial intelligence processors, Jean-Philippe (J.P.) Fricker is the creator of the biggest and fastest computer chip in the world, the Cerebras Wafer-Scale Engine. Co-founder and Chief System Architect of California company Cerebras Systems (2016), he specializes in AI systems based on neural networks. Through his company, he co-developed the largest chip ever (the size of a dinner plate), where all 850,000 cores run on the same processor. Prior to co-founding Cerebras, J.P. was Senior Hardware Architect at rack-scale flash array startup DSSD and Lead System Architect at SeaMicro where he designed three generations of fabric-based computer systems. Earlier in his career, J.P. was Director of Hardware Engineering at Alcatel-Lucent and Director of Hardware Engineering at Riverstone Networks. J.P. is a member of the Swiss Academy of Engineering Sciences SATW. He holds an MS in Electrical Engineering from École Polytechnique Fédérale de Lausanne, Switzerland, and has authored 40 patents.