Virtual Registration Package 

Architecture-Aware Precision Tuning with Multiple Number Representation Systems*

Authors: 

• Daniele Cattaneo, Politecnico di Milano, Milan, Italy
• Michele Chiari, Politecnico di Milano, Milan, Italy
• Nicola Fossati, Politecnico di Milano, Milan, Italy
• Giovanni Agosta, Politecnico di Milano, Milan, Italy
• Stefano Cherubin, Codeplay Software Ltd., Edinburgh, United Kingdom

Description: Precision tuning trades accuracy for speed and energy savings, usually by reducing the data width, or by switching from floating point to fixed point representations. However, comparing the precision across different representations is a difficult task. We present a metric that enables this comparison, and employ it to build a methodology based on Integer Linear Programming for tuning the data type selection. We apply the proposed metric and methodology to a range of processors, demonstrating an improvement in performance (up to 9x) with a very limited precision loss (<2.8% for 90% of the benchmarks) on the PolyBench benchmark suite.

 

Distilling Arbitration Logic from Traces using Machine Learning: A Case Study on NoC*

Authors:

• Yuan Zhou, Zhiru Zhang, Cornell University, Ithaca, NY
• Hanyu Wang, Shanghai Jiao Tong University, Shanghai, China
• Jieming Yin, Lehigh University, Bethlehem, PA

Description: 

Deep learning techniques have been shown to achieve superior performance on several arbitration tasks in computer hardware. However, these techniques cannot be directly implemented in hardware because of the prohibitive area and latency overhead. In this work, we propose a novel methodology to automatically "distill" the arbitration logic from simulation traces. We leverage tree-based models as a bridge to convert deep learning models to logic, and present a case study on a network-on-chip port arbitration task. The generated arbitration logic achieves significant reduction in average packet latency compared with the baselines.

 

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing Using Deep Neural Networks

Authors:

• Ahmet F. Budak, The University of Texas at Austin, Austin, TX
• David Pan, The University of Texas at Austin, Austin, TX
• Nan Sun, The University of Texas at Austin, Austin, TX
• Prateek Bhansali, Intel Corporation, Hillsboro, OR
• Chandramouli V. Kashyap, Intel Corporation, Hillsboro, OR
• Bo Liu, University of Glasgow, Glasgow, United Kingdom

Description:

In this paper, we present DNN-Opt, a novel Deep Neural Network (DNN) based black-box optimization framework for analog sizing. Our method outperforms other black-box optimization methods on small building blocks and large industrial circuits with significantly fewer simulations and better performance. This paper's key contributions are a novel sample-efficient two-stage deep learning optimization framework inspired by the actor-critic algorithms developed in the Reinforcement Learning (RL) community and its extension for industrial-scale circuits. This is the first application of DNN based circuit sizing on industrial scale circuits to the best of our knowledge.

 

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluatioin via Full-Stack Integration

Authors:

• Hasan N. Genc, University of California, Berkeley, Berkeley, CA
• Seah Kim, University of California, Berkeley, Berkeley, CA
• Alon Amid, University of California, Berkeley, Berkeley, CA
• Ameer Haj-Ali, University of California, Berkeley, Berkeley, CA
• Vighnesh Iyer, University of California, Berkeley, Berkeley, CA
• Pranav Prakash, University of California, Berkeley, Berkeley, CA
• Jerry Zhao, University of California, Berkeley, Berkeley, CA
• Daniel Grubb, University of California, Berkeley, Berkeley, CA
• Harrison Liew, University of California, Berkeley, Berkeley, CA
• Howard Mao, University of California, Berkeley, Berkeley, CA
• Albert Ou, University of California, Berkeley, Berkeley, CA
• Colin Schmidt, University of California, Berkeley, Berkeley, CA
• Samuel Steffl, University of California, Berkeley, Berkeley, CA
• John Wright, University of California, Berkeley, Berkeley, CA
• Ion Stoica, University of California, Berkeley, Berkeley, CA
• Krste Asanovic, University of California, Berkeley, Berkeley, CA
• Borivoje Nikolic, University of California, Berkeley, Berkeley, CA
• Yakun Sophia Shao, University of California, Berkeley, Berkeley, CA
• Jonathan Ragan-Kelley, Massachusetts Institute of Technology, Cambridge, MA

Description: 

DNN accelerators are often developed and evaluated in isolation without considering the cross-stack, system-level effects in real-world environments. This makes it difficult to appreciate the impact of System-on-Chip (SoC) resource contention, OS overheads, and programming-stack inefficiencies on overall performance/energy-efficiency. To address this challenge, we present Gemmini, an open-source, full-stack DNN accelerator generator. Gemmini generates a wide design-space of efficient ASIC accelerators from a flexible architectural template, together with flexible programming stacks and full SoCs with shared resources that capture system-level effects. Gemmini-generated accelerators have also been fabricated, delivering up to three orders-of-magnitude speedups over high-performance CPUs on various DNN benchmarks.

 

A Resource Binding Approach to Logic Obfuscation

Authors:

• Michael Zuzak, University of Maryland, College Park, College Park, MD
• Yuntao Liu, University of Maryland, College Park, College Park, MD
• Ankur Srivastava, University of Maryland, College Park, College Park, MD

Description:

Logic locking counters security threats during IC fabrication. Research has identified a trade-off between 2 goals of locking, error injection and SAT attack resilience. As a result, locking often cannot inject sufficient error to impact an IC while maintaining SAT resilience. We propose using architectural context available during resource binding to co-design architectures/locking configurations with high corruption and SAT resilience. We propose 2 security-focused binding/locking algorithms and apply them to bind/lock 11 MediaBench benchmarks. These circuits showed a 26x and 99x increase in the application errors of a fixed locking configuration while maintaining SAT resilience and incurring minimal design overhead.

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Accelerating EDA Algorithms with GPUs and Machine Learning

Topic Area(s): EDA, Machine Learning/AI

Session Organizers: Brucek Khailany, NVIDIA, Austin, TX; David Pan, The University of Texas at Austin, Austin, TX

Recent advancements in GPU accelerated computing platforms and machine learning (ML) based optimization techniques have led to exciting recent research progress with large speedups on many EDA algorithms fundamental to semiconductor design flows. In this session, we highlight ongoing research deploying GPUs and ML to mask synthesis, IC design automation, and PCB design at commercial EDA vendors and semiconductor design and manufacturing companies. Research into mask synthesis techniques shows the potential for GPUs to accelerate inverse lithography and for running training and inference of ML models for process modeling. In PCB layout editing, GPU-accelerated path rendering techniques can scale to millions of rendered objects with interactive responsiveness. In IC physical design, GPU-accelerated reinforcement learning for DRC fixing combined with traditional EDA optimization techniques can automate standard cell layout generation. The combination of GPUs and ML can enable large speedups and automate key EDA tasks previously seen as intractable.

Presentations include:

• Accelerating PCB Layout Editor using Modern GPU architecture for Complex Designs
• NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning

Democratizing Design Automation: Next Generation Opensource Tools for Hardware Specialization

Topic Area(s): EDA, Machine Learning/AI

Session Organizer: Antonino Tumeo, Pacific Northwest National Laboratory, Richland, WA

The growth of autonomous systems, coupled with design efforts and cost challenges brought by new technology nodes, is driving the need for generators that could quickly transition high-level algorithmic specifications to specialized hardware implementations. The necessity to explore additional dimensions of the design space (e.g., accuracy, security, system size and cooling) is further emphasizing the need for interoperable tools. This special session focuses on efforts for interoperable, modularized, and opensource tools to provide a no-human-in-the-loop design cycle from high-level specifications to ASICs and further promote novel research. The first talk introduces the status quo and CIRCT, an initiative aiming at applying MLIR and the LLVM development methodology to design automation. The second and third talks describe state-of-the-art tools, for high-level synthesis, and for logic synthesis, respectively, and discuss explorations to bridge the two. The session overviews how interoperability is achieved today, opportunities, challenges, and new perspectives enabled by community efforts.

Presentations include:

• CIRCT - Circuit IR Compilers and Tools
• Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications
• Getting the Most out of your Circuits with Heterogeneous Logic Synthesis

Design Automation of Autonomous Systems: State-of-the-Art and Future Directions

Topic Area(s): Autonomous Systems, Design

Session Organizer: Qi Zhu, Northwestern University, Evanston, IL
Shaoshan Liu, PerceptIn, Mountain View, CA

Design processes leverage various automated tools to support requirement engineering, design, implementation, verification, validation, testing and evaluation. In the domains of automotive and aerospace, design automation processes and tools have been architected and developed over the years and used to design products with established level of confidence. The recent success of Artificial Intelligence (AI) has shown great promises in improving system intelligence and autonomy for these applications. However, the adoption of those techniques also presents significant challenges for the design processes to ensure system safety, performance, reliability, security, etc. This special session will discuss essential design automation processes/tools and industrial efforts to support the development and deployment of future autonomous systems, particularly in the domains of automotive and aerospace.

Presentations include:

• Safety in Autonomous Driving: Can Tools Offer Guarantees?
• Hardware/Software Design Methods Co-Synthesis and Optimization for Autonomous Systems
• Towards Fully Intelligent Transportation through Infrastructure-Vehicle Cooperative Autonomous Driving: Challenges and Opportunities

Hardware Aware Learning for Medical Image Computing and Computer Assisted Intervention

Topic Area(s): Design, Machine Learning/AI

Session Organizer: Lei Yang, University of New Mexico, Albuquerque, NM

Deep learning has recently demonstrated performance comparable with, and in some cases superior to, that of human experts in medical image computing. However, deep neural networks are typically very large, which combined with large medical image sizes create various hurdles towards their clinical applications. In medical image computing, not only accuracy but also latency and security are of primary concern, and the hardware platforms are sometimes resource-constrained. The first two talks in this session propose novel solutions for the data acquisition and data processing stages in medical image computing respectively, using hardware-oriented schemes for lower latency, memory footprint and higher performance in embedded platforms. Considering the privacy requirement, the third talk further demonstrates a software/hardware co-exploration framework for hybrid trusted execution environment in medical image computing, preserving privacy while achieving higher efficiency than human experts.

Presentations include:

• Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
• kCC-Net for Compression of Biomedical Image Segmentation Networks
• Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment

Machine Learning Meets Computing Systems Design: The Bidirectional Highway

Topic Area(s): Design, Machine Learning/AI

Session Organizer: Partha P. Pande, Washington State University, Pullman, WA

With the rising needs of advanced algorithms for large-scale data analysis and data-driven discovery, and significant growth in emerging applications from the edge to the cloud, we need low-cost, high-performance, energy-efficient, and reliable computing systems targeted for these applications. Developing these application-specific hardware elements must become easy, inexpensive, and seamless to keep up with extremely rapid evolution of AI/ML algorithms and applications. Therefore, it is of high priority to create innovative design frameworks enabled by data analytics and machine learning that reduces the engineering cost and design time of application-specific hardware. There is also a need to continually advance software algorithms and frameworks to better cope with data available to platforms at multiple scales of complexity. To the best of our knowledge, this is the first special session at any EDA conference that explores both directions of cross-fertilization between computing system design and ML.

Presentations include:

• Mastering the Three Pillars of Accelerator Design for Deep Learning
• Functional Criticality Classification of Structural Faults in AI Accelerators
• Convergence of SoC architecture and Semiconductor Manufacturing through AI/ML Systems

A Quantum Leap in Machine Learning: From Applications to Implementations

Topic Area(s): Design

Session Organizer: Robert Wille, Johannes Kepler University, Linz, Austria

Classical machine learning techniques that have been extensively studied for discriminative and  generative tasks are cumbersome and, in many applications, inefficient. They require millions of parameters and remain inadequate in modeling a target probability distribution. For example, computational approaches to accelerate drug discovery using machine learning face curse-of-dimensionality due to exploding number of constraints that need to be imposed using reinforcement learning. Quantum machine learning (QML) techniques, with strong expressive power, can learn richer representation of data with less number of parameters, training data and training time. However, the methodologies to design these QML workloads and their training is still emerging. Furthermore, usage model of the small and noisy quantum hardware in QML tasks to solve practically relevant problems is an active area of research. This special session will provide insights on building, training and exploiting scalable QML circuits to solve socially relevant combinatorial optimization applications including drug discovery.

Presentations include:

• Building scalable variational circuit training for machine learning tasks
• Quantum Random Access Coding in Quantum Machine Learning Applications
• Drug Discovery Approaches using Quantum Machine Learning

Smart Robots with Sensing, Understanding, and Acting

Topic Area(s): Autonomous Systems, Machine Learning/AI

Session Organizer: Janardhan Rao (Jana) Doppa, Washington State University, Pullman, WA; Yu Wang, Tsinghua University, Beijing, China

The robotics industry holds enormous promise but development rates are bogged down by increasingly complex software to meet performance and safety requirements in the face of long tail events. Moreover, intelligent robots should adapt in the field to unexpected conditions that may not have ever been observed during design time. Design automation for autonomy has the potential to accelerate the rate at which we overcome these challenges (particularly outside of the autonomous driving sector which throws massive resources at the problem.) In this talk I discuss how the key tools of machine learning, AutoML, simulation, and design optimization have made an impact on systems development for two medical robotics projects - ocular microsurgery and tele-nursing - and will continue to make an impact in other sectors like automated warehouses, service robots, and agriculture.

Presentations include:

• Progress and Challenges of 3D Vision & Deep Learning in Industrial Robotics Application
• TACOS: Tactile Core with Optical String Sensor for Robotic Smart Skin

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New Frontiers in Formal and Static Verification

Description: 

In this essential session, there will be talks that focus on new explorations of formal techniques and tools by industry giants and research lab. A new approach to use formal analysis to ensure automotive SoC’s adhere to safety standards will be presented. Other presentations focus on architectural analysis, design partitioning and completeness for formal sign-off. Finally, a couple of presentations focus on static verification techniques for reset/power domains and constraint based clock-domain crossing sign-off that circumvent error-prone waiver mechanism.

Presentations:

• Ensuring Completeness of Formal Verification with GapFree: Are we done yet?
  • Presenter(s): Ratish Punnoose
• Overlapping Checkers – A Better Substitute of End-to-End Checkers
  • Presenter(s): Sumit Kumar Kulshreshtha
• Verifying Reset and Power Domains Together
  • Presenter(s): Manjunatha Srinivas, Inayat Ali, Abdul Moyeen, Manish Bhati
• Architectural Formal Sign-Off of Compression System Data Coherency
  • Presenter(s): Anuj K. More, Sanjay Bishnoi, David K. Cassetti, Dhruv Gupta, Bhushan G. Parikh, Mark A. Yarch
• LabReplay: Efficient Replay of Post-Silicon Debug for High Performance Microprocessor Designs
  • Presenter(s): Arun Joseph, Spandana Rachamalla, Shiladitya Ghosh, Shashidhar Reddy, Pradeep Joy, Sampath Baddam, Samuel Kirchhoff, Joachim Fenkes, Wolfgang Roesner

 

Chip Design and Cloud: the Good, the Emerging, and the Potential

Description: 

In this first-of-its-kind session, you will hear multiple perspectives, from educators to researchers to practitioners on how they have leveraged cloud for their work. Cloud provides a foundational platform to accelerate silicon workflows by providing seemingly limitless capacities. Presentations in this session cover how cloud enabled enhanced delivery of academic courses, technologies to implement hybrid flows, real-world experience from a cloud-based foundry, cloud-native EDA tools or “EDA 3.0”, and finally, workloads that see oversized benefits from cloud.

Presentations:

• Cloud Infrastructure for Remote and Scalable EDA Hardware Training
  • Presenter(s)Matthew Morrison, Owain Jones, Kevin Dobie
• The Reality and Opportunities of Semiconductor Design on the Cloud
  • Presenter(s)Taeil Kim, Naya Ha, Jongho Kim, Kyungtae Do, Sangyun Kim
• Utilizing the Cloud to Increase Library Characterization Throughput and Reduce Schedule Bottlenecks
  • Presenter(s)Kenneth Chang, Dnyanesh Digraskar, Matthieu FillaudWei-Lii Tan
• NEXA: Cloud Native Platform for Collaborative Hardware Logic Design in Step-wise
• Refinement Implementation Flows
  • Presenter(s)Arun Joseph, Sampath Baddam, Shashidhar Reddy, Balaji Pulluru, Pradeep Joy, Ajay Gopalakrishnan, Shiladitya Ghosh, Arvind Haran, Anthony Saporito, Matthias Klein, Wolfgang Roesner
  • New file system to automatically "spill" workloads across Datacenter and Cloud
    Presenter(s)Alok Sinha, Rajeev Prasad, Jasmin Ajanovic

 

All Routes Lead to Closing Timing

Description: 

Timing closure is the final stage of physical implementation, and where some of the most complex challenges can be encountered, creating critical schedule risk. This session covers methods to help ease timing closure, including optimization of routing layer usage, removal of pessimism from margins, quick/accurate parametrized block placement, and accelerated hierarchical ECO generation.

Presentations:

• Enabling Hierarchical Flattened Functional ECO Flow for Quality Patch Generation with Runtime Benefits
  • Presenter: Sidharth Ranjan Panda
• Middle of Layer Routing Enablement for Increasing Routing Resource
  • Presenter(s): SungOk Lee, Dayeon Cho, Sangdo Park, Yeongyeong Shin, Joonyoung Shin, Sua Lee, Hyung-Ock Kim, Sangyun Kim
• Methodology for Accurate Analysis of Dynamic Voltage Drop Induced Clock Jitter for Improved PPA
  • Presenter(s): Mathew Kaipanatu

 

Innovative Solutions for Simulation and Registers

Description: 

In this session, you will learn a variety of innovative automation techniques for test/debug, verification and validation of SoC designs.

Presentations:

• Machine Learning Based Efficient Regression Test Framework in SOC Verification
  • Presenter(s): Jicheon Kim, Daewoo Kim, Seonil B. Choi
• DIMM Level Verification Methodology for DRAM Custom DFT
  • Presenter(s): SeaEun Park, ByeongJun Bae, SeoHa Yang, IJae Kim, YounSik Park, JungYun Choi
• Get more out of your UVM register Layer!
  • Presenter(s): Pavan Yeluri, Ranjith Nair
• Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
  • Presenter(s): Elliot Gin, Anthony Cabrera, Joshua Loo, Kiel Boyle, Scott Nelson, Kyle Balston
• Novel end to end Non-coherent access mechanism on X86 SOC
  • Presenter(s): Manoj Kumar Munigala, N. Madhusudhan, Surinder Sood, Harshal Mumaikar

 

Is Your Product Secure? - An IP Driven Approach to Product Security

Presentations:

• High Bandwidth All-Digital Clock and Data Recovery Architecture
  • Presenter(s)Ankur Bal, Rupesh Singh
• Comprehensive processor security verification: A CIA problem
  • Presenter(s)Ashish Darbari
• PUF-based HRoT for Supply Chain Security
  • Presenter(s)Evans Yang, Meng-Yi Wu, Lawrence C. Liu

 

Embedded Systems! Projects and Solutions

Description: 

Embedded systems have become a necessity in every aspect of our daily life. Embedded systems design and deployment pose significant challenges in the areas of compute, power, privacy, security, connectivity, scalability and reliability. DAC Embedded systems track brings together embedded system software developers, IC designers, security experts and product managers to analyze and discuss current and future trends in the embedded systems field. In this Embedded systems session we will be discussing the challenges in security, real-time software design, Machine learning hardware accelerators, and performance modeling software design challenges.

Presentations:

• Monica​ - On-chip Monitoring Systems Characterization ​
  • Presenter(s): Giacomo Valente, Federica Caruso, Luigi Pomante, Tania Di Mascio
• “Debug in/on/with the Virtual Platform” – Please Clarify!
  • Presenter(s): Jakob Engblom
• BLOF:A Binary Group List based Low Overhead Index Structure and Fast File Management Method
  • Presenter(s): Lei Qiao, Jingjing Jiang, Bo Liu, Bin Gu, Zhi Ma, Mengfei Yang

 

Exploring the New Waves

Description: 

Explore topics from multiple domains of system design considerations to debug and integration for bringing your solutions to life. Engage to see if they make a splash with your curiosity.

Presentations:

• Virtual Environment for Developing Reinforcement Learning and Its application for thermal management
  • Presenter(s): Wook Kim
• Thermal-aware SOC floorplanning method based on a customized Deep-Q Network algorithm
  • Presenter(s): Taekeun An
• Signal Integrity aware HBM3 6.4Gbps interface Channel Optimization
  • Presenter(s): Tae Yun Kim, Soo Hyang Jeon, Chan Min JoSung Wook Moon
• Optical and Thermal Simulations for Integrated III-V/Si Heterogeneous Lasers on Silicon Photonics System
  • Presenter(s): Stanley Cheung, Antoine Descos, James Pond, Karthik Srinivasan, Stephen Pan, Norman Chang, Di Liang, Raymond Beausoleil
• Systematic Generation and Refresh of Standard Cell Abutment Database
  • Presenter(s): Anuradha Ray, Veny Mahajan
• Silicon Debugging Using Function Failure Oriented Path Delay Fault Vectors
  • Presenter(s): Keunsoo Lee, Jaehyeon Kang, Sungmin Oh, Yun HeoIlryong Kim, Khader Abdel-Hafez, Girish Patankar, Ruifeng Guo, Tae-Jin JungYong, Joon Kim

 

Novel Methods for Clocking and Functional Safety

Description: 

Clocking continues to be an important aspect of chip development, end to end functional safety is increasingly becoming more important. This session explores novel methods in both of these important aspects of chip design.

Presentations:

• Practical Method for Clock Domain Crossing Using Simulation-Based Path Extraction
  • Presenter(s): YoungRok Choi, Hyungjung Seo, So-Jung Park, ByongWook Na, Younsik Park, Jung Yun Choi
• A Novel Clock Gating Design and Verification Methodology to Ensure Safe Power Optimization
  • Presenter(s)Hao Chen, Ang Li, Suhas Prahalada, Howard Yang, Miguel Gomez-Garcia, Jonathan E. Schmidt, Leo Sporn
• Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
  • Presenter(s): Jae-Gon Lee, Wookyeong Jeong, Jaeyoung Lee, Byung Su Kim, Se Hun Kim, Young Duk Kim, Youngsan Kim, Yonghwan Kim, Sung Hoon (Ryan) Shim, Byeongho Lee, Jong-Jin Lee, Hoyeon Jeon, Younsik Choi, Joonseok Kim
• Accelerating mutation coverage measurement by using concurrent fault simulator
  • Presenter(s): Kota Sakai, Kenichi Otsuka, Fumitaka Fukuzawa, Shintaro Imamura
• Analog Fault Simulation for Automotive Sensor Designs
  • Presenter(s): Soohyun Kim, Yun Heo, Seokyong Park, Seongyeop ParkIlryong Kim, Sungjin Park, Kwangsoo Seo
• Efficient Data Exchange Towards Faster Functional Safety Development
  • Presenter(s)Shivakumar Chonnad, Vladimir Litovtchenko

 

Performance, Aging, Reliability - Key Analyses

Description: 

Learn and engage on managing performance - aging, power delivery and squeezing the last bit of performance while saving on area

Presentations:

• Efficient System PDN Analysis Methodat Pre-Layout Stage
  • Presenter(s): Seungki Nam, Jungil Son, Jeewon Kwon, Sumant Srikant, Haemin Lee, Sungwook Moon
• Aging aware Static Timing Analysis
  • Presenter(s): Sangwoo Han, Chirayu Amin
• Machine Learning based IR Drop Prediction on ECO Revised Designs for Faster Convergence
  • Presenter(s): Sashank Nishad Santanu Kundu, Manoranjan Prasad
• Simultaneous Design Methodology of High Speed & High Density Cell Libraries Using Two Different Rows in Single Design
  • Presenter(s): Dayeon Cho, SungOk Lee, Sangdo Park, Hyung-Ock Kim, Sungyoul SeoIngeol Lee, Sangyun Kim

 

Solidifying your SOC beyond Design

Description: 

Does a solid design in itself guarantee solid end product? With SOC Design methodologies well understood, often times teams face challenges in terms of having robust Silicon due to power/performance, test coverage and reliability related issues. In this session, experts will talk about some of the key factors that can be considered during design phase of the Chip to solidify the Silicon. We will look at techniques used by some of the experienced engineers to improve effects of aging and reduce variability challenges, ways to improve power and performance of your designs and key considerations while integrating Mixed-Signal IPs.

Presentations:

• Input Qualification Methodology Helps Achieve System Level Power Numbers 8x Faster
  • Presenter(s): Mohammed Fahad, Rohit Komatineni, Richard Langridge, John Reed
• Diagnostic Coverage of Memory IP with Fault Injection Simulation using TestMAX CustomFault Simulator
  • Presenter(s): Kedar Janardan Dhori, Rakesh Panemangalore Shenoy, Atul Bhargava
• Strategy for Mixed Signal IP Integration to Accelerate High-Quality SOC Development
  • Presenter(s): Gaurav Kumar Varshney, Shruti Kasetty

 

Solving Power Challenges at the Front End

Description: 

This session covers various low power design techniques and power reduction methodologies to achieve most optimal power budgets. In this session, audience will learn about recent innovations in low power domain related to coverage mechanism, workload management and advancement in the field of power and performance.

Presentations:

• Scoring Vectors for IR Sign-off Using Power-Weighted Coverage Metrics
  • Presenter(s): Huei-Shan Lin, Arti Dwivedi
• Designing IP To Achieve Optimal Low Power Using Protocol Defined Low Power States
  • Presenter(s): Saleem Mohammad, Venkataraghavan Krishnan, Shivakumar Chonnad
• Power Minimization for peak power and improved GPU sustainability
  • Presenter(s): Saurabh Shrimal, Jiaze Li, Yadong Wang, Bagus Wibowo
• Power Minimization of MCM/2.5D Chip-2-Chip communication interface
  • Presenter(s)Muhammad waqas Chaudhary
• WOW: Approximate WOrkload Watcher
  • Presenter(s): Junghwan Oh, Sunwook Kim, Manhwee Jo, Wooil Kim
• A comprehensive UPF coverage methodology to avoid late Si Issues
  • Presenter: Rohit Sinha

 

Tune in to the Clocks!

Description: 

Clock design continues to be an important aspect of the overall chip design. In this session, you would come across some novel techniques used to resolve challenges in clock design during chip development.

Presentations:

• On-Chip Dynamic IR Drop Induced Deterministic Jitter Analysis
  • Presenter: Dongchul Kim
• Optimal Function Clock Aware Scan Methodology
  • Presenter(s): Chen Yuan Kao, Min Hsiu Tsai
• Accurate glitch noise analysis considering impact of secondary aggressors
  • Presenter: Hyungoo Kim

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Autonomous Robot Design:  How can EDA help?

Organizer: 

• Iris Bahar (Brown University)

Moderator: 

• Iris Bahar  (Brown University)

Panelists:  

• Hadas Kress-Gazit Cornell University
• Sonia Chernova, Georgia Tech
• Sabrina Neuman, Harvard University
• Shaoshan Liu, Perceptin

 

Quantum Computing: An Industrial Perpective

Organizer: 

• Michael Niemier (Notre Dame)

Moderator: 

• Robert Wille (Johannes Kepler University Linz)

Panelists: 

• Leon Stok, IBM
• Krysta Svore, Microsoft
• Austin Fowler, Google

 

Homomorphic Computing as a foundational technology:  Theory, Practice, and Future Business 

Organizer: 

• Yiorgos Makris, UT Dallas

Moderator: 

• Mihalis Maniatakos, New York University

Panelists:  

• Kurt Rohloff, Duality
• Kim Laine, Microsoft Research
• Ingrid Verbauwhede, KU Leuven
• Shafi Goldwasser, MIT

Environmentally-Sustainable Computing

Organizer: 

• Carole-Jean Wu, Facebook & Arizona State U.

Moderator: 

• Carole-Jean Wu

Panelists: 

• Srilatha (Bobbie) Manne, Facebook
• Karen Strauss, Microsoft
• Fahmida Bangert, ITRenew
• David Brooks, Harvard
• Andrew Byrnes, Micron