2024 TechTalk Speakers

Juan Rey, Vice President of Government Programs, Siemens

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The Evolution of the Digital Twin in Semiconductor Design

Tuesday, June 25 | 11:15 am - 12:00 pm

 

 

 

 

Jay Vleeschhouwer, Senior Industry Analyst Covering Engineering and Enterprise Software, Griffin Securities

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A View from Wall Street

Monday, June 24 | 10:15 am - 11:00 am

We will examine the financial performance and key business metrics of the EDA industry through 2023, as well as the material technical and market trends and requirements that have influenced EDA business performance and strategies. Among the trends, we will again examine the progression of semiconductor R&D spending and how the market value of the publicly held EDA companies has evolved. Lastly, we will provide our updated financial projections for the EDA industry for 2024 through 2026.

ABOUT: Mr. Vleeschhouwer has over four decades of research experience. He is a senior industry analyst covering Engineering and Enterprise Software, responsible for fundamental research of companies under coverage, including the regular publication of proprietary company and industry reports and detailed company and industry financial modeling. Principal industry reports include The Software Standard (software industry commentary, news, data, and analysis) and The State of EDA (quarterly in-depth review of electronic design automation). Ranked by Refinitiv Starmine Analyst Awards (U.S.) #1 in "top stock pickers" for software (2020). He has been regularly invited to present at software and other industry conferences, in addition to broadcast media appearances and other print and online media

Dylan Patel, Chief Analyst, SemiAnalysis

Designing an ASIC for the Generative AI Era

Tuesday, June 25 | 10:15 am - 11:00 am

The presentation will cover what is required to design an ASIC for the Generative AI Era. It will cover the compute, networking, and memory constraints of generative AI as well as what companies are doing to push beyond it with optics, packaging, and system level design.

ABOUT: Coming soon.

 

 

 

Tom Hackenberg, Principal Analyst for Computing and Software in the Semiconductor, Memory and Computing Division, Yole Intelligence

shownChiplets - The Next Generation Chip Design Trend Beyond Moore's Law

Wednesday, June 26 | 10:15 am - 11:00 am

The next stage of integrated circuit manufacturing is disaggregation or breaking up the design of large chips into smaller units. These smaller units typically represent a unique function. The advantages are shorter design time, lower cost, easier drop-in inclusion of already available designs, increased modularity and scalability, and fewer manufacturing defects. This technique is especially well suited for leveraging the heterogeneous nature of large processors, coprocessors, system on chip (SoC) and integrated memory solutions, but the evolution of this trend is likely to spread throughout IC design.

This presentation is designed to provide a brief introduction to the nature of chiplet design and why it is so important at this time. The technical details will be presented in moderation including teardown examples of current chiplet solutions and which end-systems include them. The presentation will touch on technology advances that need to evolve to facilitate this approach. We will provide a market penetration and a five-year forecast for chiplet-based design strategies. We will provide longer views of the evolution to include such ICs as graphics, AI, and other accelerators, FGPAs, microcontrollers and other processors. We will conclude with why we think this trend is essential to the future of the semiconductor industry and design automation.

ABOUT:

Tom Hackenberg is a Principal Analyst for Computing and Software in the Semiconductor, Memory and Computing Division at Yole Intelligence, part of Yole Group. Tom is an industry leading expert reporting on markets for semiconductor processors including CPUs, MPUs, MCUs and DSPs, SoCs, GPUs and discrete accelerators, FPGAs, and configurable processors since 2006. Tom is also well-versed in related technology trends including AI and edge computing, IoT, heterogeneous processing, chiplets, as well as vertical markets like Automotive, Computing and Telecommunications where processor trends play a significant role.

Tom has appeared as a presenter on these topics at associated events as the Chiplet Summit, OCP ODAS Workshop on Chiplets, Rosenblatt’s Age of AI Scaling, System-on-Chip Conference, Vision and AI Summit, Xilinx Adapt: Automotive: Anywhere, Yole’s Live Market Briefings and as well as custom proprietary presentations. He can also be found quoted or bylined in news and trade publications such as Cision, Computerworld, Design and Reuse, EE|Times & EE|Times Asia, Fierce Electronics, Insider, Semi Engineering, VentureBeat, and more for expertise on the processor market.

Tom worked with market-leading processor suppliers developing both syndicated and custom research. He holds a BSEE/BSECE from the University of Texas at Austin specializing in Processors and FPGAs.

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