Hail Caesar, We Who Are About to Present Our Research, Salute You

Join us at DAC 2023 to watch our fierce Engineering Track Poster Gladiators battle to see who will emerge as the winner of the DAC Gladiator Poster Award. 

This new program recognizes the hard work and preparation the poster submitters have completed. Each Poster Gladiator finalist will be given 5-minutes in the DAC Pavilion on either the Monday or Tuesday of DAC to present their submitted and approved poster presentation in a speed round. Presenters will be presenting in front of a panel of expert industry judges. In addition to the judges, the audience will also be partly responsible for determining the fate of each gladiator and deciding the winner. 

Poster gladiators will be judged on the following criteria:

  • Engineering Tracks reviewer scores
  • Originality and creativity of the work being presented
  • Clarity and writing style
  • Impact of the gladiator's ideas and work

Battle MC - Brian Fuller, ARM


  • Michael (Mac) McNamara, Adapt IP
  • Harry Foster, Siemens
  • Rob Oshana, Analog
  • Rob Aitken, Synopsys

Meet the 2023 Poster Gladiators


Poster Title:  Gladiators
Novel Hierarchical IREM Sign-off Flow using ROM Dongyoun Yi, Samsung Electronics, Seonghun Jeong, Samsung Electronics, Byunghyun Lee, Samsung Electronics
Early IR Drop Prediction Using Machine Learning for Power Grid Anil Dsouza, Intel Technology India Pvt Ltd, Anantha Krishnan, Intel Technology India Pvt Ltd, Ayan Roy Chowdhury, Intel Technology India Pvt Ltd
Pre-Silicon Power Side-channel Security Verification for Crypto IPs Amitabh Das, AMD, Emrah Karagoz, AMD, Geethu Sathees Babu, Ansys, Sreeja Chowdhury, Ansys
Automation Framework Based IP/Subsystem Integration Verification in SoC - A Systematic Approach for Integration Quality Signoff Yogeshwaran Shanmugam, Texas Instruments, Aswin B, Texas Instruments, Karthik Rajakumar, Texas Instruments
Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module

Lakshmanan Balasubramanian, Texas Instruments, Penchalkumar Gajula, Texas Instruments, Avinash Chaudhary, Texas Instruments, Krthika Nanya, KarMic Design Private Limited, Sumantha Manoor, Texas Instruments, Gaurav Kumar Varshney, Texas Instruments

Static Analysis for Early Detection and Efficient Debug Hormoz Yaghutiel, Alif Semiconductor, Guru Shindaghatta, Real Intent, Kanad Chakraborty, Real Intent
Reuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis Amit Goldie, Synopsys, Himanshu Kathuria, Synopsys, Suresh Babu Barla, Synopsys, Vrinda Achithan Padmakumari, Synopsys
An Accurate System Level Transient Voltage Droop Analysis Methodology for High Performance GPGPU Power Delivery Network Yuanyuan Ling, Iluvatar, China, Ling Sun, Iluvatar, China, Tieqing Chen, Iluvatar, China, Zhenhua Gan, Iluvatar, China, Shixuan Que, Iluvatar, China, Shuqiang Zhang, Iluvatar, China,, Xiaoxia Zhou, Iluvatar, China
A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent Priya Meharde, STMicroelectronics Pvt. Ltd., Aditya Sharma, STMicroelectronics Pvt. Ltd., Anil Nagendra, STMicroelectronics Pvt. Ltd., Priyanshi Shukla, Cadence Design Systems
High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios Alexander Pivovaraov, AMD, Vidhu Joshi, AMD, Mehdi Sadi, AMD
HW Security Path Validation Using Formal Methods: Intel Case Studies Alex Levin, Intel, Sayak Ray, Intel
Unified Solution for CAD Development of Analog, Digital & Mixed Signal IPs Lippika Parwani, STMicroelectronics, Bhupendra Singh, STMicroelectronics, Gaurav Goel, STMicroelectronics, Anil-kumar Dwivedi, STMicroelectronics
Requirement tracing for Design Flow in communication protocols IP Marco Meuli, STMicroelectronics
Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF Rohit Kumar Gupta, STMicroelectronics, Etienne Maurin, STMicroelectronics, Sebastien Marchal, STMicroelectronics, Jean-Arnaud Francois, STMicroelectronics, Oliver Minez, STMicroelectronics, Chiranjeev Kumar Grove, STMicroelectronics
Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization Moonsu Kim, Samsung Electronics, SLSI Business, Jaeyoung Lim, Samsung Electronics, SLSI Business, Jaehyeon Kang, Samsung Elenctronics, SLSI Business, Changho Han, Samsung Electronics, Foundry Business, Asheesh S. Baghel, Synopsys, Wenwen Chai, Synopsys, Li Ding, Synopsys
Automated Clock Analysis, Skew Group Generation & CT Verification Raghubeer Singh, STMicroelectronics, Harshil Niranjanbhai UPADHYAY, STMicroelectronics, Anil Yadav, STMicroelectronics
Packet Processing Scaling a flexible scalable approach Pushkar A. Upadhye, Marvell Technology
















Congratulations to the 2022 DAC Poster Gladiator Award Winners! 




Congratulations to Romain Feuillette from GlobalFoundries for your poster battle victory with the poster, "Machine Learning Techniques for PDK Development Efficiency!"

The 2022 Poster Gladiator will receive a full conference pass to the 2023 DAC being held July 10 -14 at Moscone West in San Francisco and asked to be a judge at next year’s Poster Gladiator session.







Congratulations to the 2021 DAC Poster Gladiator Award Winners!




Congratulations to our Poster Gladiator Winners from proteanTecs (Evelyn LandmanAlex BurlakNir Sever, and Uzi Baruch) with their poster:

Deep data for faster silicon bring-up, characterization, and qualification with higher confidence