DAC Poster Gladiator Award

New for DAC 2021, the Designer, IP and Embedded Systems (Engineering) Tracks Poster ONLY presentations became eligible to win the prestigious DAC Gladiator Poster Award. Winners of the award were announced and recognized on Tuesday, December 7 in the DAC Pavilion. This new program recognizes the hard work and preparation the poster submitters have completed. Each Poster Gladiator finalist was given 5-minutes in the DAC Pavilion on either the Monday or Tuesday of DAC to present their submitted and approved poster presentation in a speed round. Presenters will be presenting in front of a panel of expert industry judges. Judges voted along with the audience to select the 2021 DAC Poster Gladiator.

Congratulations to the 2021 DAC Poster Gladiator Award Winners!

Congratulations to our Poster Gladiator Winners from proteanTecs (Evelyn Landman, Alex Burlak, Nir Sever, and Uzi Baruch) with their poster:

Deep data for faster silicon bring-up, characterization, and qualification with higher confidence

The 2021 Poster Gladiator will receive a full conference pass to the 2022 DAC being held July 10 -14 at Moscone West in San Francisco and asked to be a judge at next year’s Poster Gladiator session.

Thank you to our 2021 judges:

Mac McNamara, Adapt-IP – DAC Past chair and Past Designer/IP Chair
Rob Aitken, Arm – DAC Past Chair
Zhuo Li, Cadence – DAC Past Chair and Past Designer/IP Chair
Mark Kraeling, GE Transport – Embedded Systems Chair
Moderator - Brian Fuller, Arm

See all 2021 Poster Gladiator contestants:

Poster Title:	Gladiators	Poster Gladiator Presentation Day	Poster Gladiator presentation time	Poster Session Date (day they are presenting in the Poster Hall)
Enhanced Analytics and Reporting for Triage and Sign-off Timing	Kerim Kalafala, Richard Taggart	Monday, December 6	4:40	Wednesday, December 8^th
Shift-left Post-Silicon verification with Speed and Accuracy	Oscar Monroy, Jitendra Aggarwal	Monday, December 6	4:45	Wednesday, December 8^th
Enhanced Hyperscaling of Data Centers using In-Chip Monitoring & Sensing Fabrics	Ramsay Neil Allen, Firooz Massoudi	Monday, December 6	4:50	Wednesday, December 8^th
Routability Improvement Methodology Using Multiple Standard Cells with Various Pin Location	Sua Lee, Joonyoung Shin, Hyung-Ock Kim, Sangdo Park, Jooyeon Kwon, Yeongyeong Shin, Yongcheul Kim, Sangyun Kim	Monday, December 6	4:55	Tuesday, December 7^th
A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs	Blaise Pascal Tine, Fares Elsabbagh	Monday, December 6	5:00	Wednesday, December 8^th
Abstraction- An efficient methodology for RTL & Low-Power Signoff in SoC Design	Rohit Sinha	Monday, December 6	5:10	Wednesday, December 8^th
Towards measuring layout pattern coverage: a Machine Learning Approach	Hui Fu	Monday, December 6	5:15	Wednesday, December 8^th
Deep data for faster silicon bring-up, characterization, and qualification with higher confidence	Tamar Naishlos, Shubharthi Datta, Alex Burlak	Tuesday, December 7	4:40	Monday, December 6^th
End-to-End Solution for structured implementation of high-speed data buses	Subhadarshini Behera, Dheeraj Tuteja, Shubham Agarwal, Shishir Saran Rai	Tuesday, December 7	4:45	Monday, December 6^th
Expediting Data Converter Layouts using Design Planning & Analysis (DPA) Automation	Colin Thomson, Vishesh Kumar, Atul Bhargava	Tuesday, December 7	4:50	Wednesday, December 8^th
Algorithm to RTL: A Faster Path to Implementation	Russell Klein, Anoop Saha	Tuesday, December 7	4:55	Monday, December 6^th
Innovative Techniques to Accelerate Error Handling Verification of Complex Systems	Peter Graniello, Neha Rajendra, Bhushan G. Parikh	Tuesday, December 7	5:00	Monday, December 6^th
Robust Timing Analysis And Optimization under Parametric On-Chip Process Variation	Jaeyoung Lim, Li Ding, Yun Heo, Jegil Moon, Wenwen Chai, Moon-Su Kim, Ilryong Kim	Tuesday, December 7	5:05	Monday, December 6^th
A flexible SAR-ADC IP for multiple technodes	Torsten Reich, Benjamin Prautsch, Marcel Jotschke	Tuesday, December 7	5:10	Wednesday, December 8^th
Hybrid Emulation Methodology for SSD Design	Byeongwook Bae, Seunghan Lee, Sangho Park, JaeWoo Im, Jungyun Choi, Kyungsu Kang, Byunghoon Lee, SungGil Lee	Tuesday, December 7	5:15	Wednesday, December 8^th

DAC 59

July 10-14, 2022
San Francisco

Exhibit at DAC

DAC is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP).

Become an Exhibitor

DAC Blog

Keep up to date with the Design Automation Conference.

Stay Connected