Hail Caesar, We Who Are About to Present Our Research, Salute You
Join us at #62DAC to watch our fierce Engineering Track Poster Gladiators battle to see who will emerge as the winner of the DAC Gladiator Poster Award.
This new program recognizes the hard work and preparation the poster submitters have completed. Each Poster Gladiator finalist will be given 5-minutes in the DAC Pavilion on either the Monday, Tuesday, or Wednesday of DAC to present their submitted and approved poster presentation in a speed round. Presenters will be presenting in front of a panel of expert industry judges. In addition to the judges, the audience will also be partly responsible for determining the fate of each gladiator and deciding the winner.
Poster gladiators will be judged on the following criteria:
- Engineering Tracks reviewer scores
- Originality and creativity of the work being presented
- Clarity and writing style
- Impact of the gladiator's ideas and work
Battle MC - Brian Fuller, ARM
Judges
Harry Foster, Siemens, DAC General Chair 2021
Mac McNamara, Adapt IP, DAC General Chair 2017
Vivek De, Intel, DAC General Chair 2024
Rob Aitken, NAPMP, General Chair 2019
Ambar Sarkar, Nvidia, Past Engineering Track Chair, 62nd DAC Research Panel Chair
Meet the 2025 Poster Gladiators
| Poster Title: |
Gladiators |
Date |
Time |
| Streamlined RTL Clock Management: A Python Framework for Clock Tracing, Clock Spec Verification and STA Constraint Generation |
Tejas Dhanajirao Salunkhe (Texas Instruments); Faeq Hussain (Texas Instruments) |
Monday |
5:05 pm - 5:12 pm |
|
Physical Design Independent-IR solver for early first cut SoC PG analysis
|
Prateek Pendyala (Google); Jingwei Zhang (Google); T Govindaswamy Rahul Sai (Google)
|
Monday |
5:13 pm - 5:20 pm |
|
Innovative and Cost-Effective Approach to ESD Reliability Verification in the Cloud
|
Gazal Singla (Siemens); Ertugrul Demircan (NXP Semiconductors)
|
Monday |
5:21 pm - 5:28 pm |
|
Optimizing Network Storage for AI-Powered EDA Deployments
|
Prathna Sekar (Keysight Technologies)
|
Monday |
5:28 pm - 5:35 pm |
|
Design Quality Improvement Through Automation
|
Sagar Jogur (Texas Instruments); Mangesh Dhantole (Texas Instruments)
|
Monday |
5:36 pm - 5:43 pm |
|
A new methodology to generate a multitude of SoC configurations quickly
|
Fernand Da Fonseca (Arm Ltd.); Chouki Aktouf (Defacto Technologies); Valentin Boyer (Defacto Technologies); Mael Rabe (Defacto Technologies)
|
Monday |
5:44 pm - 5:51 pm |
|
ENZO: Comprehensive DFT Methodology for MCU class of devices
|
Arshdeep Singh (Texas Instruments); Jahnavi Pragada (Texas Instruments); Vishal Diwan (Texas Instruments); Yogeshwaran Shanmugam (Texas Instruments)
|
Tuesday |
5:05 pm - 5:12 pm |
|
IC Folding for Enhanced Performance in Homogeneous RF-AMS Systems
|
Parv Malhotra (Cadence Design Systems); Neha Agrawal (Cadence Design Systems); Hitesh Marwah (Cadence Design Systems); Mike Lin (Cadence Design Systems); Arnold Ginetti (Cadence Design Systems); Praveen Pillai (Cadence Design Systems); Jignesh Patel (Global Foundries); Aditya Melinamane Ramesha (Global Foundries)
|
Tuesday |
5:13 pm - 5:20 pm |
|
Accelerating Chip Design with AI-Powered Additive Learning for Deep Sub-Micron Technologies
|
Mohamed Atoua (Siemens); Amit Bansal (Microchip); Raju Raasa (Microchip); Ajaj Ansari (Siemens); Vishal Kulshrestha (Microchip)
|
Tuesday |
5:21 pm - 5:28 pm |
|
Confidentiality Assurance: A Key Component of Hardware Security
|
Varun Sharma (Real Intent Inc.); Vikas Sachdeva (Real Intent Inc); Vinod Viswanath (Real Intent Inc.)
|
Tuesday |
5:28 pm - 5:35 pm |
|
AI-ML meets SPICE to achieve 6-sigma Accuracy: A Revolution in Statistical Analysis
|
Aditya Vasisth (ST Microelectronics); Rajesh Narwal (ST Microelectronics); Pravesh Kumar Saini (ST Microelectronics); Prayes Jain (Cadence Design Systems)
|
Tuesday |
5:36 pm - 5:43 pm |
|
Fast-tracking PCIe Verification in an SoC by automating the testbench using triple Check test-suite
|
Subramanian R (Samsung Semiconductor); Sekhar Dangudubiyyam (Samsung Semiconductor); Naga Swetha Maddulapalli (Samsung Semiconductor); Naveen Srivastava (Samsung Semiconductor); Harshal Kothari (Samsung Semiconductor)
|
Tuesday |
5:44 pm - 5:51 pm |
|
Clock H-tree exploration in BSPDN
|
Jongbeom Kim (Samsung Electronics); Dayeon Cho (Samsung Electronics); Wook Kim (Samsung Electronics); Ki-ok Kim (Samsung Electronics); Hyung-Ock Kim (Samsung Electronics)
|
Wednesday |
2:05 pm - 2:12 pm |
|
Silicon Lifecycle Management in Automotive Design
|
Rajnish Garg (STMicroelectronics); Amerjeet Kumar (STMicroelectronics); Harshil Niranjanbhai Upadhyay (STMicroelectronics); Anil Yadav (STMicroelectronics); Anil Dwivedi (STMicroelectronics)
|
Wednesday |
2:13 pm - 2:20 pm |
|
Advanced State Space Tunneling: Debug Your Formal Complexity Using Waveforms!
|
Erik Seligman (Cadence Design Systems); Lars Lundgren (Cadence Design Systems); Mariane Goncalves (Cadence Design Systems); Gustavo Junquiera (Cadence Design Systems); Tulio Leao (Cadence Design Systems); Gabriela Bahia (CCadence Design Systems); Hakan Hjort (Cadence Design Systems); Craig Deaton (Cadence Design Systems); Varun Ramesh (Tenstorrent); Varun Ramesh (Tenstorrent)
|
Wednesday |
2:21 pm - 2:28 pm |
|
A Safety Centric approach to Functional Verification of Dual Core Lock-Step Designs
|
Mohammad Anas Rashid (Samsung Semiconductor India R&D); Suharini C (Samsung Semiconductor India R&D); Ratan Deep (Samsung Semiconductor India R&D); Harsh Setia (Samsung Semiconductor India R&D); Sarang Kalbande (Samsung Semiconductor India R&D)
|
Wednesday |
2:29 pm - 2:36 pm |
|
Reducing Top Level Verification Cycle of High Frequency PLLs with Enhanced Fast-SPICE Technology
|
Ankit Gupta (STMicroelectronics); Atul Bhargava (STMicroelectronics); Nitin Jain (STMicroelectronics); Prayes Jain (Cadence Design Systems); Ankur Bal (STMicroelectronics)
|
Wednesday |
2:37 pm - 2:42 pm |
|
Building a Parallel Simulation Kernel for Faster & Better Virtual Platforms
|
Jakob Engblom (ASTC)
|
Wednesday |
2:43 pm - 2:50 pm |
| AWARD SELECTION |
|
Wednesday |
3:00 pm - 3:45 pm |
Congratulations to the 2023 DAC Poster Gladiator Award Winners!
Congratulations to Marco Meuli from STMicroelectronics for your poster battle victory with the poster, 'Requirement Tracing for Design Flow in Communication Protocols IP.'
The 2023 Poster Gladiator will receive a full conference pass to the 2024 DAC being held June 23-27 at Moscone West in San Francisco and asked to be a judge at next year’s Poster Gladiator session.
Congratulations to the 2022 DAC Poster Gladiator Award Winners!
Congratulations to Romain Feuillette from GlobalFoundries for your poster battle victory with the poster, "Machine Learning Techniques for PDK Development Efficiency!"
The 2022 Poster Gladiator will receive a full conference pass to the 2023 DAC being held July 10 -14 at Moscone West in San Francisco and asked to be a judge at next year’s Poster Gladiator session.
Congratulations to the 2021 DAC Poster Gladiator Award Winners!
Congratulations to our Poster Gladiator Winners from proteanTecs (Evelyn Landman, Alex Burlak, Nir Sever, and Uzi Baruch) with their poster:
Deep data for faster silicon bring-up, characterization, and qualification with higher confidence