Hail Caesar, We Who Are About to Present Our Research, Salute You

Join us at DAC 2022 to watch our fierce Engineering Track Poster Gladiators battle to see who will emerge as the winner of the DAC Gladiator Poster Award. 

This new program recognizes the hard work and preparation the poster submitters have completed. Each Poster Gladiator finalist will be given 5-minutes in the DAC Pavilion on either the Monday or Tuesday of DAC to present their submitted and approved poster presentation in a speed round. Presenters will be presenting in front of a panel of expert industry judges. In addition to the judges, the audience will also be partly responsible for determining the fate of each gladiator and deciding the winner. 

Poster gladiators will be judged on the following criteria:

  • Engineering Tracks reviewer scores
  • Originality and creativity of the work being presented
  • Clarity and writing style
  • Impact of the gladiator's ideas and work

Meet the 2022 Poster Gladiators

Poster Title:  Gladiators
A Scalable Framework to Validate Interconnect-Based Firewalls to Enhance SoC Security Coverage Ashutosh Mishra, Intel India Pvt Ltd
A Unified IP QA methodology to Improve Validation Coverage and Throughput Lippika Parwani, STMicroelectronics; Jean-arnaud FRANCOIS, STMicroelectronics; Geetanjali Sharma, STMicroelectronics; Wei-Lii Tan, Siemens EDA; Lionel Couder, Siemens EDA
Automated Timing Degradation Recovery in Incremental Tape-Out of High-Speed CPU Design Gopalakrishnan Sadagopan, Intel India Private Limited; Senthil Ravi,, Intel India Private Limited
Billion Instance Timing Sign-off Tim Helvey, Marvell; David Lawson, Marvell
Design-Technology Co-Optimization to Mitigate the Technology Impact of Context-Based Timing in Standard Cell library

Veny Mahajan, ST Microelectronics Pvt Ltd; Anand Mishra, ST Microelectronics Pvt Ltd

Design Timing Effects of Layer-to-Layer Interconnect Skew Ayhan Mutlu, Synopsys; Duc Huynh, Synopsys; Jian-Feng Chen, R&D Engineering; Li-Chung Hsu, R&D Engineering; Li Ding, Synopsys
Dynamic CDC Verification with Enhanced Jitter Modeling in Synchronizers Youngchan Lee, Samsung Electronics; Vikas Sachdeva, Real Intent
Is Front-End Analog Design Automation an NP-type or Simply a P-type Problem ? Ramy Iskander, Intento Design
Left Shift Mechanism to Mitigate Gate Level Asynchronous Design Challenges Rohit Kumar Sinha, Intel Technology Private Ltd; Kavya Kotha,  Intel Technology Private Ltd
Machine Learning Techniques for PDK Development Efficiency Nolan Pavek, GlobalFoundries; Romain Feuillette, GlobalFoundries; Vivienne Miller, GlobalFoundries
Minimize Power Consumption with A Novel Power ECO Flow Jianfeng Liu, Samsung Electronics Co. Ltd; Eunju Hwang, Samsung Electronics Co. Ltd; YeongYeong Shin, Samsung Electronics Co. Ltd; Seokhoon Kim, Samsung Electronics Co. Ltd; Jun Seomun, Samsung Electronics Co. Ltd; Sangyun Kim, Samsung Electronics Co. Ltd
Optimal and Efficient Power Aware Verification Framework for Low Power Mixed-Signal SoC Sooraj Sekhar, Texas Instruments (India) Pvt. Ltd.;Harsh Kumar Sharma, Texas Instruments (India) Pvt. Ltd.; Akshay Revankar, Carnegie Mellon University; Siddharth Sarin, Texas Instruments (India) Pvt. Ltd.; Pavan Kumar Kulkarni, Texas Instruments (India) Pvt. Ltd.; Ruchi Shankar, Texas Instruments (India) Pvt. Ltd.; Harish Maruthiyodan, Texas Instruments (India) Pvt. Ltd.; Shalini Eswaran, Texas Instruments (India) Pvt. Ltd.; Gaurav Kumar Varshney, Texas Instruments (India) Pvt. Ltd.; Lakshmanan Balasubramanian, Texas Instruments (India) Pvt. Ltd.
Pre and Post Silicon Analysis in the Design and Validation of AI Enabled High Performance Microprocessors Nagu Dhanwada, IBM Corporation;  Karthik Swaminathan, IBM Research; Kartik Acharya, IBM Systems; Khajista Fattu, IBM Systems; Ramon Bertran, IBM Research; Anurag Umbarkar,  IBM Systems
Successive Refinement– An approach to decouple Front-End and Back-end Power Intent Rohit Kumar Sinha, Intel Technology Private Ltd; Kavya Kotha, Intel Technology Private Ltd
Towards an Automated Workflow for Link-level Exploration and Optimization in the Domain of All-to-All Optical Networks Luca Ramini, Hewlett Packard Labs; Ahsan Alam, Ansys Canada
Using Formal Verification Signoff for Digital IP David Vincenzoni, ST Microelectronics

 

 

Congratulations to the 2021 DAC Poster Gladiator Award Winners! 

Congratulations to our Poster Gladiator Winners from proteanTecs (Evelyn LandmanAlex BurlakNir Sever, and Uzi Baruch) with their poster:

Deep data for faster silicon bring-up, characterization, and qualification with higher confidence

The 2021 Poster Gladiator will receive a full conference pass to the 2022 DAC being held July 10 -14 at Moscone West in San Francisco and asked to be a judge at next year’s Poster Gladiator session.