| Poster Title: |
Gladiators |
| Novel Hierarchical IREM Sign-off Flow using ROM |
Dongyoun Yi, Samsung Electronics, Seonghun Jeong, Samsung Electronics, Byunghyun Lee, Samsung Electronics |
| Early IR Drop Prediction Using Machine Learning for Power Grid |
Anil Dsouza, Intel Technology India Pvt Ltd, Anantha Krishnan, Intel Technology India Pvt Ltd, Ayan Roy Chowdhury, Intel Technology India Pvt Ltd |
| Pre-Silicon Power Side-channel Security Verification for Crypto IPs |
Amitabh Das, AMD, Emrah Karagoz, AMD, Geethu Sathees Babu, Ansys, Sreeja Chowdhury, Ansys |
| Automation Framework Based IP/Subsystem Integration Verification in SoC - A Systematic Approach for Integration Quality Signoff |
Yogeshwaran Shanmugam, Texas Instruments, Aswin B, Texas Instruments, Karthik Rajakumar, Texas Instruments |
| Correct-by-Construct Netlist Based Integration Flow for Mixed-Signal Low Power Multi Chip Module |
Lakshmanan Balasubramanian, Texas Instruments, Penchalkumar Gajula, Texas Instruments, Avinash Chaudhary, Texas Instruments, Krthika Nanya, KarMic Design Private Limited, Sumantha Manoor, Texas Instruments, Gaurav Kumar Varshney, Texas Instruments
|
| Static Analysis for Early Detection and Efficient Debug |
Hormoz Yaghutiel, Alif Semiconductor, Guru Shindaghatta, Real Intent, Kanad Chakraborty, Real Intent |
| Reuse of Lint Waivers: An Approach to Relay Knowledge & Guide Synthesis |
Amit Goldie, Synopsys, Himanshu Kathuria, Synopsys, Suresh Babu Barla, Synopsys, Vrinda Achithan Padmakumari, Synopsys |
| An Accurate System Level Transient Voltage Droop Analysis Methodology for High Performance GPGPU Power Delivery Network |
Yuanyuan Ling, Iluvatar, China, Ling Sun, Iluvatar, China, Tieqing Chen, Iluvatar, China, Zhenhua Gan, Iluvatar, China, Shixuan Que, Iluvatar, China, Shuqiang Zhang, Iluvatar, China,, Xiaoxia Zhou, Iluvatar, China |
| A Structured way of Communication in Layout Design Flow through Virtuoso Design Intent |
Priya Meharde, STMicroelectronics Pvt. Ltd., Aditya Sharma, STMicroelectronics Pvt. Ltd., Anil Nagendra, STMicroelectronics Pvt. Ltd., Priyanshi Shukla, Cadence Design Systems |
| High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios |
Alexander Pivovaraov, AMD, Vidhu Joshi, AMD, Mehdi Sadi, AMD |
| HW Security Path Validation Using Formal Methods: Intel Case Studies |
Alex Levin, Intel, Sayak Ray, Intel |
| Unified Solution for CAD Development of Analog, Digital & Mixed Signal IPs |
Lippika Parwani, STMicroelectronics, Bhupendra Singh, STMicroelectronics, Gaurav Goel, STMicroelectronics, Anil-kumar Dwivedi, STMicroelectronics |
| Requirement tracing for Design Flow in communication protocols IP |
Marco Meuli, STMicroelectronics |
| Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF |
Rohit Kumar Gupta, STMicroelectronics, Etienne Maurin, STMicroelectronics, Sebastien Marchal, STMicroelectronics, Jean-Arnaud Francois, STMicroelectronics, Oliver Minez, STMicroelectronics, Chiranjeev Kumar Grove, STMicroelectronics |
| Combined FEOL/BEOL Process Sweet Spot Search for Chip Performance Optimization |
Moonsu Kim, Samsung Electronics, SLSI Business, Jaeyoung Lim, Samsung Electronics, SLSI Business, Jaehyeon Kang, Samsung Elenctronics, SLSI Business, Changho Han, Samsung Electronics, Foundry Business, Asheesh S. Baghel, Synopsys, Wenwen Chai, Synopsys, Li Ding, Synopsys |
| Automated Clock Analysis, Skew Group Generation & CT Verification |
Raghubeer Singh, STMicroelectronics, Harshil Niranjanbhai UPADHYAY, STMicroelectronics, Anil Yadav, STMicroelectronics |
| Packet Processing Scaling a flexible scalable approach |
Pushkar A. Upadhye, Marvell Technology |