Members of RISC-V International will be delivering numerous presentations and hosting discussions and tutorials at the annual Design Automation Conference (DAC) 2020, taking place from Monday, July 20 through Friday, July 24, showcasing RISC-V’s incredible momentum since its inception ten years ago at the University of California, Berkeley.
The presentations, discussions and tutorials will focus on new and exciting developments and implementations from the RISC-V community, spotlighting how the instruction set architecture (ISA) is well-equipped to handle newer, more demanding workloads and ushering in a new era of silicon design and processor innovation.
Please see below to find out more about the RISC-V sessions taking place at the virtual event and be sure to follow RISC-V on Twitter for real-time updates.
We look forward to “seeing” you there!
MONDAY, JULY 20
Tutorial 6: System Level Power Analysis with Unified Power Models
Date: Monday, July 20, 10:30 a.m. to Noon PT
Speakers: Nagu Dhanwada of IBM Corp.
Rhett Davis of North Carolina State Univ.
David Ratchkov of Thrace Systems
Organizer: Jerry Frenkil of Silicon Integration Initiative, Inc.
About: The demand for increased power efficiency in both wired and wireless applications continues to grow unabated. This demand has generated considerable interest in low power design methods that have become well established at the RTL, gate, and physical, levels. The tutorial will begin with an overview of the standard. This overview will be followed by detailed descriptions of the various data representations and modeling levels, elaborating on the applicability of each to different modeling situations. The novel UPM/2416 system level semantics will be illustrated using specific examples of power models for common IP blocks, such as a memory and a RISC-V processor. Bottom-up models, based on design data and power contributors, and top-down models, based on measured or simulated data, will be described in detail. The examples will include details of how UPM/2416 power data models inter-operate with UPF/1801 power state models.
TUESDAY, JULY 21
Designer Track Poster Live Text Chat Q&A
Date: Tuesday, July 20, 7:30 – 8.30 a.m. PT
Session: 126.53 – Security and Trust Assurance of RISC-V Open-source Cores RocketCore and OpenHW CV32E
Authors: Blake Buschur of Edaptive Computing, Inc.; Sven Beyer of OneSpin Solutions GmbH
RISC-V Revolution and Momentum
Date: Tuesday, July 20, 9:20 – 10 a.m. PT
Speaker: Calista Redmond of RISC-V International
About: RISC-V has ushered in a profound shift in the technical and business models for microprocessors. Let's talk about the revolution and the many facets of engagement and strategic adoption around the world, across industries, and within existing and new domains. Learn more about RISC-V International's role in leading the revolution and disrupting the status quo.
RISC-V Pavilion Member Company Presentations
A Walk Through PolarFire® SoCs Memory Subsystem
Date: Tuesday, July 20, 10:30 – 10:50 a.m. PT
Speaker: Tim Morin of Microchip Technology, Inc.
21st Century Challenges Require 21st Century Solutions
Date: Tuesday, July 20, 11 – 11:20 a.m. PT
Speaker: Hanan Moller of UltraSoC
Formal Verification of RISC-V Cores
Date: Tuesday, July 20, 11:30 – 11:50 a.m. PT
Speaker: Salaheddin Hetalani of OneSpin Solutions
Building a High Powered AI/ML accelerator using a RISC-V CPU core with Vector Extension
Date: Tuesday, July 20, Noon – 12:20 p.m. PT
Speaker: John Min of Andes Technology
What’s Next for RISC-V? Vectors, Verification, and Value-Added Extensions
Date: Tuesday, July 20, 12:30 – 12:50 p.m. PT
Speaker: Simon Davidmann of Imperas Software
Advanced Power Techniques/RISC-V Design and Validation
Date: Tuesday, July 20, 1:30 – 3 p.m. PT
Chair: Dave Rich of Mentor
About: Power consumption continues to be a critical issue in any modern design. The first half of this session will present a variety of new techniques related to low-power design and validation. Another topic that has taken the industry by storm in recent years is the revolutionary open-source RISC-V ISA. In the second half of this session, it will discuss some new ideas in design and validation related to this architecture.
Session: 27.4* – RISCV-DV: An Open Source Verification Platform for RISC-V Processors (Best Paper Candidate)
Authors: Tao Liu and Richard Ho of Google, Inc.
Session: 27.5 – A RISC-V Secure Element for PQC: “Fantasy Chip” Codesign Approach
Author: Markku-Juhani O. Saarinen of PQShield
WEDNESDAY, JULY 22
Tackling IP Challenges for Next Generation Technologies Like AI/ML/5G
Date: Wednesday, July 22, 1:30 – 3 p.m. PT
Chair: Chirag Dhruv - Advanced Micro Devices, Inc., San Jose, CA
About: In this session, speakers will share their experience about how they tackle power reduction challenges including in-house and third-party IPs, discuss how key performance improvements have been achieved on AI/ML workloads and how a robust verification of IPs like RISC-V can be achieved with formal verification techniques, and how it can apply ML to help improve performance by optimizing Phys.
Session: 61.6 – Universal Formal Verification for RISC-V Processors
Author: Ashish Darbari - Axiomise Ltd.
THURSDAY, JULY 23
Open Source Trends Leveraging RISC-V Technology (Special/Invited Session)
Date: Thursday, July 23, 10:30 a.m. – Noon PT
Chair: Alessandro Piovaccari - Silicon Labs
Organizer: Rick O'Connor - OpenHW Group
About: The electronics industry is embracing open-source processor technologies like RISC-V at an unprecedented rate. This creates a need to develop a deep ecosystem to support the adoption of the RISC-V ISA. This includes various components including processor implementations, verification suites, software middleware, stacks, and tools – all aligned to move the architecture forward. In this session, it will discuss two communities that are driving this technology forward; the CHIPS Alliance and the Open Hardware Group. In addition, it will provide an industry update on the incorporation of RISC-V technology into microcontroller applications.
Session: 3.1 – Open Source Processor IP for High-Volume Production SoCs: CORE-V Family of RISC-V Cores
Author: Rick O'Connor of OpenHW Group
Session: 3.2 – Harnessing the Energy of Open Source Hardware Collaboration with the CHIPS Alliance
Author: Zvonimir Bandić of Western Digital Corp.
Session: 3.3 – Software PPA Metrics: Results from Real-World MCU Applications
Author: Joe Circello of NXP Semiconductors
A Stitch in Time Saves AI: Tailoring AI for Hardware Platforms
Date: Thursday, July 23, 3:30 – 5 p.m. PT
Chair: Siva Hari of NVIDIA Corp.
Co-Chair: Vikas Chandra of Facebook
About: The papers in this session present approaches to tailor deep neural networks to a wide range of hardware platforms, including RISC-V, GPUs, FPGAs, emerging memory devices and compute-in-storage systems.
Session: 88.1 – Extending the RISC-V ISA for Efficient RNN-Based 5G Radio Resource Management
Authors: Renzo Andri and Luca Benini of ETH Zurich; Tomas Henriksson of Huawei Technologies Co., Ltd.
You can check out the full DAC 2020 program here. To schedule a meeting with RISC-V International or a member organization, please email: RISC-V@racepointglobal.com.
Stay up-to-date about the latest RISC-V news by following the RISC-V International on LinkedIn, Twitter and YouTube.